Design Of NoC-based Spike Neural Network Communication Architecture

In recent years,the field of neural computing has developed rapidly,and remarkable progress has been made in many fields such as pattern recognition,associative memory,signal processing,automatic control,combination optimization,fault diagnosis,and computer vision.Among them,the spiking neural network is favored by major research institutions and companies due to its rich space-time characteristics,high-efficiency transmission characteristics,and event-driven low power consumption.The traditional von Neumann architecture is difficult to support spiking neural networks,so people have launched hardware implementation designs for spiking neural networks,such as the“Truenorth” neural network chip launched by IBM,“Loihi” launched by Intel in 2018,and Tsinghua University's “Tianji”,“Darwin” chip of Zhejiang University,etc.The most critical and most challenging part of the hardware implementation of spiking neural networks is to design a parallel communication architecture that supports millions of neurons.Although research institutions continue to introduce pulsed neural network chips,their communication architecture has certain shortcomings.For example,due to the limitation of hardware resources,the fan-in and fan-out of neurons are limited,the supported network topology is not comprehensive enough,and the global communication network is not comprehensive.The transmission efficiency is low,so this article will further carry out the research on the communication architecture of the Spike Neural Network based on No C.This article aims at designing a high-performance spiking neural network communication architecture,and addressing the problems of low communication efficiency and large fan-in and fan-out limitations of the existing spiking neural network communication architecture,from the internal structure of the nerve core,synaptic storage,routing algorithms,etc.Exploring the angle of research and designing a spiking neural network communication architecture that supports arbitrary topologies,flexible fan-in and fan-out,and efficient transmission.The main research content and innovations of this article are as follows:(1)Design and realization of nerve core.Aiming at the problems of low computational efficiency,large amount of data,and limited fan-in and fan-out supported by hardware resources,this paper divides the synapse memory module and the input pulse buffer unit into 6 small SRAM blocks,combined with scheduling The unit controls the reading of 6SRAMs to ensure that the reading process does not conflict,and realizes the simultaneous operation of 6 physical neurons,which improves the calculation efficiency;by sharing the address of the presynaptic neuron and nucleus,the synaptic storage required by the neuron is reduced space;by adding a row to store the neuron's synapse end address before the synapse storage of each neuron,the synaptic storage space can be fully utilized to support larger fan-in and fan-out of neurons or a larger number of small fan-in neurons.(2)Design and implementation of asynchronous network on chip.Because the pulse neural network is based on event-driven characteristics,in order to reduce the power consumption of the pulse neural network,data is only transmitted when the pulse event occurs.This paper designs a completely asynchronous global on-chip communication network based on the four-phase data binding protocol.In order to avoid deadlock and improve transmission efficiency,the router design of the network-on-chip adopts virtual channel technology.The router is composed of input unit,routing calculation,virtual channel distribution unit,switch distribution and crossbar switch.When there is data competition,the polling arbitration rule is used for arbitration output.In addition,a time step synchronization module is designed to avoid the invalid waiting or missing data of the neural network.(3)Aiming at the one-to-many transmission characteristics of spiking neural networks,this paper proposes an efficient multicast routing algorithm based on the shortest path.The algorithm proposes a new way of dividing subsets,reducing the number of data packets,reducing network traffic,and reducing power consumption;by setting different priorities for each node's data packets,the network traffic is balanced;A new header microchip compression scheme reduces design complexity and reduces the length of data packets.Finally,through verification,the proposed new SP multicast routing algorithm has lower delay and lower power consumption than the classic column-based shortest path multicast routing algorithm.