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Design And Implementation Of SAR Transceiver Based On Packet Architecture

Posted on:2022-01-05Degree:MasterType:Thesis
Country:ChinaCandidate:J Q YangFull Text:PDF
GTID:2518306572496474Subject:IC Engineering
Abstract/Summary:PDF Full Text Request
With the continuous development of network technology,the demand of various services for digital communication network is more and more high.Packet switching is the common switching technology in digital communication network.Packet switching is a transmission switching mode with packet as the basic unit.One of the key technologies for packet switching is SAR(Segmentation and Reassembly),which can segment and reassemble the data code stream as a constant rate.Data segmentation and packet reorganization are implemented by SAR transmitter and SAR receiver respectively.The dynamic decision mechanism based on DSM(Delta Sigma Modulator)is used to determine the net charge length in the SAR transmitter.The data rate is characterized by the dynamic changing net charge length,and the data is divided into net charges according to the net charge length.Packet is mainly composed of header and net charge.The header contains valid information such as time stamp,packet number and length of net charge.In the SAR receiver,FIFO is used to cache packet data,judge the delay time according to the time stamp,control packet reading and adjust packet delay time.According to the packet number and other information,the lost packet length is recovered,and the original data stream is reorganized from the packet and cached.According to the rate recovery mechanism,the data of the corresponding beat number is read in T cycles,and the output data stream processed by this mechanism can better reflect the original data stream rate.Based on the in-depth study of Data stream segmentation and recombination of ODU(Optical Data Unit)and Flexe(Flexible Ethernet Instance),the paper realizes the circuit of Data stream partitioning into packets and packets regrouping into Data streams.In this paper,each module of the SAR transceiver is simulated,integrated and verified by FPGA.The simulation and verification results show that the designed circuit can divide and recombine the data stream of ODU and FLEXE instance with the transmission rate of100 Gbps correctly,and monitor the packet data and its delay time.The paper has a strong reference value for the realization of data code stream segmentation and packet recombination based on packet switching.
Keywords/Search Tags:Packet switching, Segmentation, Rate recovery, Reassembly
PDF Full Text Request
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