Implementation Of SURF Feature Descripor Based On FPGA

As a hotspot of computer vision,image feature extraction has been widely used in many scenes in the industry,agriculture and medicine,which greatly facilitates people's life and work.The SURF(Speeded-Up Robust Features)image feature point extraction algorithm has excellent robustness,but its computational complexity is high,and it is difficult to meet the high real-time requirements on the traditional PC platform.Field Programmable Gate Array(FPGA)devices have the characteristics of high real-time performance.The accelerated design of the SURF feature point extraction algorithm based on FPGA is favored by many researchers and has a wide range of application prospects.In response to the real-time requirements of the SURF image feature point extraction algorithm,this dissertation designs the SURF feature descriptor hardware acceleration circuit,and designs the integral image storage circuit as an interface to connect with the existing feature detection hardware circuit of the research group,and realizes a complete SURF feature point extraction system based on FPGA.The feature description circuit includes two parts:the main direction generation and the descriptor generation.For the main direction generation part,in order to reduce the reading time of the cached data,this dissertation calculates the Haar response value of the sampling points in the neighborhood of the feature points based on the sliding window structure.At the same time,in order to avoid the repeated statistics of the overlapping area data during the rotation of the sector domain,a fast accumulation and summing circuit is designed.For the descriptor generation part,in order to avoid data overlap between adjacent sub-domains,this article implements sub-domain division by inserting a register chain in the line buffer that stores the Haar response value of the sampling point,and combines the register chains belonging to the same sub-domain into a sliding Window to calculate the cumulative value of the Haar response of the sub-domain.In the integral image storage circuit,in order to reduce the hardware overhead caused by separately buffering the sliding window data,this design realizes the cache sharing of feature detection and feature description circuits by expanding the size of the sliding window.In this dissertation,on the FPGA platform of Xilinx Zynq XC7Z100,the SURF feature detection and feature description circuit are combined to build a complete SURF feature point extraction system,and the standard test set of the University of Oxford is used to simulate the SURF feature descriptor circuit.The robustness of the hardware algorithm for SURF feature extraction is evaluated.The experimental results show that,compared with the software results,the root mean square error of this design is within 1.79×10^-5,the accuracy is good,and the robustness in fuzzy scenes is basically the same as that of the SURF algorithm in Open CV.The robustness in the scenes of rotation skew,fine texture skew,angle rotation,illumination transformation,and compression transformation is similar to that of the SURF algorithm in Open CV.At a clock frequency of 100 MHz,the system implemented in this dissertation can achieve a minimum processing speed of 106fps and a maximum of 156 fps for images with a resolution of 640×480.