Study And Implementation Of Lightweight Pedestrian Detection YOLO Algorithm Based On FPGA

Pedestrian detection,as one of the hot issues in computer vision,has been widely used in many practical scenarios,such as unmanned driving systems,assisted driving systems,intelligent video surveillance,and robotics.At present,the pedestrian detection algorithm based on convolutional neural network(CNN)surpasses the traditional pedestrian detection algorithm by a large advantage,but due to the complex structure and the large amount of calculation of CNN,it is difficult to realize real-time application on the embedded platforms with insufficient resources.Real-time application.You only look once(YOLO)algorithm,as one of the current pedestrian detection algorithms with the best speed and performance,still has the problems of large memory requirements and high computational complexity.In order to solve the above problems,this thesis carries out the lightweight research and design of YOLOV4-tiny pedestrian detection algorithm through the analysis of the idea of lightweight,proposes YOLOV4-light lightweight algorithm,and verifies the effectiveness of lightweight algorithm on the Caltech-USA data set.In order to make the improved algorithm convenient for hardware application,hardware acceleration design and test verification are carried out on the field programmable logic gate array(FPGA).The main work is as follows:(1)In order to reduce the memory requirement and computational complexity of the network model,an operation module based on extended convolution and depthwise separable convolution is proposed,which improves the convolution operation process.According to the memory access cost(MAC),the extended convolution and pointwise convolution are further optimized,which decreases the unnecessary MAC and the number of network layers.So as to further achieve better lightweight effect,the design of width multiplier is adopted in the entire network,In the precess of the width multiplier experiment,the feature pyramid network(FPN)is further studied,and the original feature path is improved.(2)To reduce the complexity of hardware application,it is proposed to use depthwise convolution to replace maximum pooling,which decreases the number of computing modules needed for algorithm hardware implementation.In order to reduce the logic resources needed in hardware implementation,the activation function of network is improved.So as to speed up the inference verification on hardware,a 16-bit fixed-point inference scheme is designed to decrease the requirement of computating and storage resources.According to the reasoning process of the network,the software and hardware division scheme of the network is designed.Based on the above work,the hardware verification of YOLOV4-light algorithm is realized through the co-design of the software and hardware.The proposed YOLOv4-light algorithm has been tested on Caltech USA dataset.The experimental results show that the memory requirement of the YOLOV4-light algorithm has been reduced by 89.3%,the computational complexity has been decreased by 87.9%,and the accuracy is has only been reduced by 0.48%.The fixed-point results of the proposed algorithm show that the results of the fixed-point scheme are basically consistent with the results of the software algorithm,which proves the effectiveness of the fixed-point scheme.The hardware verification result of the proposed algorithm shows that the fixed-point output result of FPGA is basically consistent with the output result of the software algorithm,which proves the correctness of the hardware implementation function.