FPGA Solder Joint Based On Improved LS-SVM Esearch On Failure Assessment Method

With the rapid development of integrated circuits,BGA packaged FPGA,namely field programmable logic gate array,with its powerful function,short development cycle,small size and other advantages,is more and more applied to space technology,mobile communication,radar electronics and other fields.In order to solve the problems of failure assessment methods of FPGA welding joint,such as unable to provide accurate information,less sample data and low timeliness,based on the research of many scholars at home and abroad,combined with GA(genetic algorithm),an improved LS-SVM is proposed The main research contents of this paper are as follows: 1Firstly,this paper introduces the research background and significance of solder joint reliability of BGA packaged FPGA,expounds the current research status of solder joint reliability at home and abroad,and analyzes the importance of solder joint failure and condition evaluation of FPGA.Then,the failure mode and failure mechanism of four failure models of FPGA solder joint,including crack,fracture,void and loss,are analyzed,and the parameter optimization process of LS-SVM model by GA is discussed.Then,the damaged FPGA is used for simulation test,and the simulation results are displayed in Multisim The BIST circuit simulation model is built in the simulation software.By simulating the information of FPGA solder joint impedance value,it is transformed into the low-level duration of capacitor voltage fault waveform,so as to obtain the data set of solder joint resistance value,test frequency and low-level duration of capacitor voltage fault waveform,and establish a three-dimensional data model.Then the IP core of SJ BIST is downloaded to the de2 hardware platform of Altera company to verify its feasibility.Through the conversion relationship between the impedance value information at the solder joint and the low-level duration of the capacitor voltage fault waveform,the health status information of the solder joint can be obtained by using the duration of the low-level.The experimental results show that the health or fault status of the FPGA solder joint is consistent with the simulation test structure.Finally,in order to quickly and effectively evaluate the failure of FPGA solder joint,according to the incremental range of low-level duration of capacitor voltage fault waveform in FPGA solder joint module,the solder joint fault is divided into three levels.Genetic algorithm is used to optimize the kernel function and regularization parameters of least squares support vector machine The three-dimensional data model is classified and evaluated by measuring machine.The results show that the method can accurately evaluate the fault level of FPGA solder joint,so as to realize the state evaluation of FPGA solder joint failure.