Neural Network Architecture And Circuit Design For Low Power Keyword Recognition

Keyword recognition technology is currently becoming the mainstream human-computer interaction method,especially in wearable devices,the Internet of Things and other applications.These mobile portable devices have strict requirements for low power consumption.Therefore,it is very important to design a keyword recognition product that meets the requirements of low-power applications.Based on this,this thesis is proposed with a specific circuit for Quantized Convolutional Neural Network(QCNN)for Keyword Spotting(KWS).The design is optimized from the two aspects of algorithm and circuit to reduce the power consumption of the KWS system.Firstly,from the algorithm level,the KWS model based on the recognition of ten keywords is optimized to reduce the calculation complexity and resource consumption,including: the optimized feature extraction module based on Mel Frequency Cepstrum Coefficient(MFCC),and keyword recognition based on quantized convolutional neural network in training.Secondly,a special circuit processing module for QCNN is designed to reduce the circuit's calculation and storage power consumption from the circuit level.The main work include: 1: Taking full advantage of the characteristics of the voice data stream,a framework based on framed state machine control is proposed.Through the framed pipeline and time division multiplexing operations of the data stream,the power consumption and area required by the computing unit are reduced.2: According to the characteristics of the neural network,a data path mode based on the data mixed multiplexing mode is designed to reduce the power consumption of data handling.3: According to the characteristics of the parameters,a computing array that supports both 4-bit and 8-bit calculation modes and data zero-hop calculation is proposed to reduce the power consumption of data calculation.This thesis is verified with he TSMC 22 nm ULP process,and completed with the QCNN architecture and circuit design for low-power KWS.The circuit simulation results show that: at a working frequency of 0.6MHz and a voltage of 0.72 V,the power consumption of the QCNN circuit module in the 8-bit calculation mode is 9.08?W;the power consumption in the 4-bit calculation mode is 5.26?W,which is obvious lower than similar designs.