Research On BCNN Algorithm For Small And Medium Image Recognition And Mapping To Hardware

With the improvement of hardware computing power,convolutional neural network(CNN)has made important contributions in many fields such as digital image processing.Meanwhile,binary convolutional neural network(BCNN)has attracted much attention in lightweight because of its advantages of extracting features without multiplication operations.However,designing an efficient hardware-oriented BCNN structure is not simple by the characteristics of the binary algorithm,and the biggest problem is that the algorithm makes up for the loss caused by binarization by improving the network structure is not necessarily beneficial to the hardware implementation.The research goal of this thesis is to overcome this problem and collaborative study binary networks from two aspects of binary algorithm and hardware acceleration.At the algorithm level,an efficient multi-layer binary neural network scheme for hardware mapping is designed.The scheme is mainly to improve the traditional binary convolution into two-layer convolution of binary group convolution and binary depthwise convolution,and adopt improved channel rearrangement and accumulation design in the forward propagation process to achieve high efficiency mapping.The binary network has further reduced the storage of weights and effectively solved the problem of hardware accelerator feature storage through the above improvements.It has achieved a recognition accuracy rate of not less than 86.5% and95% on the CIFRA-10 and MNIST data sets,respectively.Meanwhile,the improved algorithm is also mapped to hardware,the hardware acceleration of multilayer network is achieved by interlayer flow and intergroup reuse,and replaces the traditional two-input serial calculation with three-input parallel XOR to reach lower hardware.At the same time,all double-layer convolution operations are calculated using a lookup table,in order to improve the efficiency of hardware resource utilization.The final design of the accelerator on the FPGA processing speed of small and medium-sized images reached 542.5 FPS,the IP core power consumption is only 1.255 W,which meets the design requirements of the thesis.The lightweight binary neural network accelerator designed in this thesis can achieve a higher processing frame rate on the FPGA platform with fewer resources,which fully meets the requirements of real-time recognition applications.The image recognition system with practical application value can be constructed by using the accelerator in this thesis on the terminal equipment.