Deep Learning Model Compression And Acceleration For Image Processing Based On FPGA

With the increasing demand for image processing,the role of deep learning is significantly improved.Many deep learning networks play a crucial part in image processing,production,security,and other fields,such as YOLO,SSD,and other target detection and recognition networks.Which bring great convenience for tasks like automatic driving and behavior recognition.However,the huge parameters of deep learning networks also put forward requirements for computing power consumption.A large number of parameter calculations not only affect the real-time performance of the calculation results but also bring huge energy consumption to the embedded end with low power consumption.Aiming at the problem of poor real-time performance and high power consumption of embedded deep learning networks for image processing,a new deep learning model compression method was proposed based on deep learning networks,FPGA technology,and embedded technology.Moreover,the deep learning model was accelerated on FPGA,and a set of target detection and recognition device based on FPGA acceleration was designed,which solved the problems of poor real-time performance and high power consumption of deep learning networks in embedded terminals.The main work of this article is summarized as follows:1.The platform and method of image processing deep learning models on embedded terminals were investigated and summarized in detail.After fully understanding the advantages and disadvantages of the deep learning networks on the embedded terminal,the overall design framework of this paper was proposed.2.Aiming at the problem that parameters of deep learning networks are too large and the application were limited on embedded side,a channel pruning convolutional neural network model compression method based on channel sparsity was proposed.This method defined the sparseness function of each channel in convolutional neural networks.By calculating the sparseness index of each channel,the channel sparse characteristics of the convolutional neural network were judged,and the channel sparseness was used to perform channel pruning.The regularized sparse channel function was constructed by combining the L2 regularization with the sparsity function.This pruning method was applied to the CIFAR-10 and CIFAR-100 datasets to VGGNet,Google Net,and Res Net.On the three classic networks,while maintaining the accuracy of the model,the parameters of the model were compressed to 2.1 MB,1.7 MB,and 0.64 MB,respectively.3.In terms of the problem that high power consumption and poor real-time performance of deep learning networks implemented on the embedded side,the target detection algorithm YOLO accelerator based on the Winograd minimum filter algorithm was designed in this paper.Convolution operations in YOLO algorithm was improved from multiplication and addition method to Winograd method,which greatly reduced the multiplier resource consumption when accelerating the YOLO model.Using Zynq as the platform to accelerate the YOLO algorithm guaranteed low power consumption of accelerating deep learning models on embedded terminals.4.The target detection and recognition device based on XILINX Zynq7020 FPGA was designed by this paper.The startup time of the embedded operating system was aiso optimized.And the hardware platform construction including external interfaces design such as USB interface,HDMI interface,Ethernet port,and PCB performs layout and wiring was fully completed.From image acquisition and processing to display,a target detection platform based on FPGA acceleration was designed and implemented.The regularized sparse channel pruning method proposed in this paper can compress deep learning networks and greatly reduce the number of parameters on the premise of ensuring the accuracy of the network.The acceleration of deep learning networks on FPGA was not only good in real time,but also can greatly reduce the power consumption of networks operation.Finally,a target detection and recognition device based on FPGA acceleration was designed.This work provided a new idea for many occasions such as factory inspection,drones,and traffic monitoring.