Optimized Design And Implementation Of AES Encryption/Decryption System Based On FPGA

With the development of information society,information security is threatened increasingly.The emergence of encryption technology has ensured information security,using encryption algorithms to encrypt data can prevent information leakage effectively.Based on chaos-related theory and the AES algorithm principle,this system proposes optimization solutions for the two issues of how to improve the security of encryption/decryption and how to increase the algorithm rate without increasing a large number of resources.This system is based on the unpredictability of chaotic systems,uses the initial value of the chaotic system and the effective iterative starting round number of the chaotic system as the system key.Furthermore,the chaotic pseudo-random sequence generated based on Qi hyperchaos is used as the initial key of the AES algorithm and applied to the AES algorithm.In this way,the security of encryption/decryption can be improved;The key extension adopts separate designs for encryption and decryption.The decryption key extension still uses the conventional method,but the encryption adopts key expansion module and round-transformation in parallel.Carry out the key expansion of the round key while performing the round-transformation so that the key expansion provides the round key for the round-transformation in real time.It saves key expansion time and improves encryption speed without adding additional resources;Combining the Shift Rows module with the Sub Bytes module directly changes the bytes'output order after substitution bytes to achieve shift rows.Turn two modules into one module,use one module to complete the Shift Rows module and Sub Bytes module functions simultaneously,save the logic resources of the Shift Rows module;Reuse the Mix Columns module for encryption algorithm and decryption algorithms.Calculate the multiplication result of each byte in the finite field GF(2~8)with{02},{04}and store the result in the dual-port ROM,can directly use the look-up table to complete Mix Columns and inv Mix Columns.It can save logic consumption,reduce the amount of calculation,and improve the algorithm rate;Make the reciprocal transformation in the encryption round-transformation and decryption round-transformation of the AES algorithm into a shared module.The module can perform both the encryption round-transformation function and the decryption round-transformation function.This way can save many logical resources.Finally,this system uses Verilog HDL language to complete the system design and construction on the EP4CE30F23C8N chip of Altera's Cyclone IV series,carried out simulation verification and hardware test on the system.The test results show that this system can complete data encryption/decryption correctly.The system consumes12769 logical units,while the optimized AES algorithm only occupies 1986 logical units.Compared with encryption speed before optimization,the optimized AES algorithm's encryption speed is increased by 40%,meet the requirements of optimized design.