The Hardware Design And Verification Of Asymmetric Cryptographic Algorithm

Human society is gradually entering the information age,and information security threats are full of human lives.Cryptography can be used as one of the methods to solve information security,which ensure information security.Cryptographic algorithms can be divided into three categories: asymmetric cryptography,hash function,and symmetric cryptography.The key of an asymmetric cryptographic algorithm consists of a public key and a private key.The signer uses the public key and private key to sign,and the verifier uses the private key to verify the signature.Asymmetric cryptographic algorithms include RSA(Rivest-Shamir-Adleman),ECC(Elliptic Curve Cryptography),DF(Diffiie-Hellman),and DSA(Digital Signature Algorithm),have the characteristics of good security,slower performance,etc.They are suitable for digital signature,digital certificate authentication and other scenarios.At present,RSA and SM2 are frequently used in asymmetric cryptographic algorithms.Therefore,this paper adopts the method of hardware design to study the algorithms RSA and SM2.This article first introduces the elliptic curve algorithm and the basics of large number operations through the investigation and analysis of the current situation at home and abroad,and explains the principles of algorithm SM2,RSA.Through the encryption and decryption of algorithm RSA and algorithm SM2 signature verification analysis,the algorithm implementation adopts software and hardware co-design method to design an asymmetric cryptographic system based on SoC framework.On the hardware,the algorithm SM2 realizes dot multiplication and modular addition,subtraction,multiplication and inverse operations,and the algorithm RSA realizes modular exponentiation and modular multiplication operations.On the software,the algorithm SM2 dispatches the dot multiplication module and the modular arithmetic module in the hardware through the CPU,and the algorithm RSA realizes the CPU scheduling modular exponentiation and modular multiplication arithmetic modules.In hardware design,the algorithm RSA modular exponentiation operation adopts the RL binary expansion method,the modular multiplication operation adopts the Montgomery modular multiplication algorithm,the algorithm SM2 point multiplication operation adopts the NAFw(k)scalar multiplication algorithm,and the point doubling point operation is realized under the Jacobian domain and the prime domain.the modular inverse operation adopts the radix-4 Montgomery modular inverse algorithm,which improves the shift efficiency of the modular inverse operation and improves the entire modular inverse operation capability.The modular multiplication operation is realized through the multiplier and the modular reduction.After algorithm analysis,the resources consumed in the two algorithms are modular multiplication operations,so the two algorithms share a 256bit*256bit multiplier.The multiplier is realized by using the KO(Karatsuba-Ofman)algorithm and instantiating a 66 bit multiplier and a 512 bit adder.During the verification,a UVM verification platform suitable for the two algorithms is built,component register models are added to the verification platform,and the registers and memories in the DUT are modeled to facilitate the detection of DUT errors.Under the software VCS compilation,the DUT and the run log are observed.The results in the reference model are the same.The top layer of the algorithm hardware module and the CPU are connected through the AHB bus to form a SoC system.The algorithm is simulated before the Smart L simulation platform is completed,Finally,the chip Artix-7 series FPGA development board is selected to complete the FPGA verification.Through VCS pre-simulation and FPGA verification,both the signature verification,encryption and decryption functions of the two algorithms are realized.Finally,based on the process of SMIC 55 nm and integrated with the integrated tool DC,the integrated area is about 490Kum2,the algorithm SM2 signature verification rate is about 111 times/s,106 times/s,and the algorithm RSA encryption and decryption rate is about 11 times/s.The designed system has the characteristics of high configurability,meets the requirements of chip design,and can be applied to scenarios such as the Internet of Things.