Implementation And Verification Of Symmetric Cryptographic Algorithm

Cryptography still plays a very critical role in the context of increasingly severe information security.At present,according to the number of keys and the difference in usage methods,cryptographic algorithms are mainly divided into asymmetric cryptographic algorithms and symmetric cryptographic algorithms.The former uses private and public keys in the encryption and decryption process,while the latter uses the same key.AES and SM4 cipher algorithms are the current mainstream symmetric cipher algorithms,which have high security in information transmission.Traditional cryptographic algorithms are mostly implemented through software methods,but this method occupies more resources,has low computational efficiency and insufficient security.The hardware method can have higher computing efficiency and security,and has a higher reference value in terms of information security.Therefore,this article chooses to use hardware methods to implement AES and SM4 symmetric cryptographic algorithms.In the design of AES and SM4 symmetric cryptographic algorithm hardware modules,in view of the similarity of the two algorithms,this paper firstly designs the implementation structure based on the principles of the two algorithms.Here,innovatively adopts the realization structure that the encryption & decryption process and the key expansion process are carried out at the same time.Different from the previous key expansion operation and encryption and decryption operations performed independently,each key is stored in the register and called when needed,the new structure can greatly reduce the number of registers.According to the new implementation structure,this article also designs the required inverse key expansion algorithm,especially the AES symmetric cipher algorithm.According to the different key length,the key expansion operation is also different.Therefore,we design the inverse key expansion algorithms of AES-128,AES-192,and AES-256 respectively.Then,we optimize the(inverse)S-box of the AES and SM4 symmetric algorithms implemented in the finite field.The(inverse)S-box in the finite field is subjected to isomorphic mapping operations to make it operate in the compound domain,and the structure of the(inverse)S-box realized in the compound domain is optimized.After completing the design of the AES and SM4 hardware modules,we build a generic UVM verification platform,after which the generic verification platform is modified in a targeted manner according to the AES and SM4 algorithm hardware modules under test.With the targeted verification platform,this paper conducts functional tests on the AES and SM4 algorithm modules under test,and uses the coverage rate to determine the verification progress,and the coverage rate gradually approach 100% with the increasing number of test cases.Finally,this article synthesizes the AES and SM4 modules based on the SMIC 55 nm CMOS process and the 200 MHz clock constraint.The comprehensive area of the AES module is 51999.36,which is about 46.42 k equivalent gates.It takes 30 cycles to perform an AES?256 encryption and decryption operation,and the throughput rate can reach 856.2Mb/s;the comprehensive area of the SM4 module is 17732.4,which is about 15.83 k equivalent gates,it takes 66 cycles to perform an encryption and decryption operation,and the throughput rate can reach 287.8Mb/s.Compared with other similar designs,the throughput rate of this design can reach above the average level in the area clock,it can meets the design requirements of this design.