Design Of Energy-Efficient Acceleration For MobileNetV1

Convolutional neural network is a basic model of deep learning,which is computationally and storage-intensive.Among them,the MobileNet series network based on depthwise separable convolution is a typical representative of lightweight networks.It uses depthwise separable convolution to reduce the calculation amount and parameter amount of standard convolution to nearly 1/9,greatly reducing the network model,compared with other large-scale networks are more suitable for deployment on mobile terminals.When the general-purpose processor of the mobile terminal performs neural network reasoning tasks,there is a common problem of low energy efficiency and insufficient real-time performance.In this work,for the application scenarios of mobile terminals,a high-energy-efficiency acceleration architecture for MobileNetV1 is researched and designed.The main contents and characteristics of this thesis are as follows:1.Introduced the basic knowledge related to convolutional neural network,explained the principle of the depthwise separable convolution reduction network model,and selected the lightweight network MobileNetV1 as the acceleration object of this thesis.2.Analyzed the main structure of the MobileNetV1 network,and proposed a special instruction set with layer operations as the description object.The instruction set uses 32-bit encoding to complete all the mapping of information required for single-layer operations,the instruction set closer to the software model of the network,improving code density and providing convenience for software programming.3.Based on the instruction set,a programmable dedicated accelerator for MobileNetV1 is proposed.Aiming at the problem of low utilization of large-scale on-chip output cache,the accelerator based on the channel dimension priority data storage method,using the time locality of convolution operation,designed an iterative control that achieves efficient data reuse in small-scale input cache.The solution improves memory access efficiency and cache line utilization,and simplifies the storage structure.In addition,multiple optimization methods such as multiplexing one-dimensional multiply-accumulate arrays and implementing Re LU6 using simple floating-point comparators save the resource overhead of the accelerator.4.Evaluate the dedicated instruction set and accelerator architecture.The special instruction set of this article has the characteristics of high code density and ease of use.Under the TSMC 28nm process,the accelerator has a total area of 0.275mm~2,and at a working frequency of 1.25GHz,the total power consumption is 63.7m W,and it can perform MobileNetV1 network inference tasks at a speed of 5.0fps.