An ASIC Design For RGB-D SLAM Feature Point Matching

RGB-D simultaneous localization and mapping(RGB-D SLAM)refers to the SLAM technology that uses the RGB-D sensor as the main environmental perception device.Compared with mono or stereo SLAM,which need complex calculations to obtain the depth information,RGB-D SLAM directly obtains the depth information of pixels through the sensor,which eliminates the calculation for the depth information.Feature point matching is an important step in the RGB-D SLAM front-end visual odometer,which provides the data source for subsequent camera pose estimation.However,huge quantity of computation results in poor real-time performance of the SLAM system,which has become a bottleneck in the embedded field.In this thesis,we focus on the large amount of calculation and high operational repeatability during the process of feature point matching in the RGB-D SLAM.The matching process is divided into two parts,the rough matching and the mismatch elimination.In the rough matching part,based on the thorough analysis of the universality of binary descriptors in this field,a hardware architecture based on the hamming distance is proposed.In the mismatch matching elimination part,this thesis adopts a matching pair screening scheme based on the random sample consensus(RANSAC)algorithm,and proposes a 3D-2D RANSAC hardware architecture.Based on the above descriptions,an application specific integrated circuit(ASIC)architecture for RGB-D SLAM feature point matching system is proposed.The main research contents of this thesis are as follows:1.In this thesis,the research status of feature point matching hardware acceleration is thoroughly analyzed,and the common algorithm for the rough matching process and the RANSAC algorithm are introduced in detail.For the part of rough matching,we propose the nearest neighbor brute force matching algorithm and simplifies it's hardware implementation.For the part of mismatch elimination,a series of optimizations have been made to the RANSAC algorithm to make it more hardware friendly and the convergence of iterations is accelerated at the same time.2.An ASIC architecture of feature point matching system is proposed,which includes two parts:the rough matching circuit and the 3D-2D RANSAC circuit.In order to improve system throughput,the rough matching circuit is carefully designed to utilize the feature of Hamming distance matching tree and the matching window FIFO mechanism.The 3D-2D RANSAC circuit improves the real-time performance by reorganizing the data flow in the calculation of hypothetical model and multiplexing calculation channels with the pipeline technology,while only slightly increasing resource comsumption.Meanwhile,the self-adjustment of the number of iterations is realized through a look-up table.3.The error introduced by the above algorithm alteration is analyzed experimentally based on the TUM RGB-D dataset.In addition,the backend layout is realized with the TSMC 28 nm process.The total area of the design is about 0.2018)8)~2,and the equivalent gate number is 334 k.What's more,the total power consumption is 114.23 m W at the limit frequency of 1.25G Hz.At a working frequency of 200 MHz,this architecture can process a video stream with the image size of 640×480 at 1301 fps.