A Hardware Trojan Detection Method Based On Structural Features Of Trojan And Host Circuits

Modern IC(Integrated Circuit)design often involves third-party IP(Intellectual Property)cores,outsourced test and design services as well as third-party EDA(Electronic Design Automation)tools.This geographically highly distributed business model makes it easy for ICs to be maliciously inserted extra logic by third-party attackers,i.e.the hardware Trojan(HT).Due to the stealthy nature of HTs,it is difficult to detect HTs in circuits through the traditional functional verification.This paper proposes an HT detection technology that combines HT structural features with host circuit features.Firstly,this paper constructs an HT structural feature library covering the combinational logic HTs and the sequential logic HTs by analyzing existing HT benchmarks.Next,this paper proposes a feature matching algorithm to detect the structural features of HTs in the circuit under test and calculate the HT feature values.Then,the testability analysis of the host circuit is carried out to obtain the feature values of the host circuits.After that,the HT feature values are combined with the host feature values by dynamic weights to obtain the Trojan-host feature values.At the same time,this paper proposes an outlier determination algorithm to find outliers in the Trojan-host feature values and identify Trojan candidates.Finally,this paper proposes optimized approaches of the outlier determination algorithm based on multi-layer neural networks and the density-based clustering,respectively,to further improve the accuracy rate.Experiments on 64 Trust Hub benchmarks show that all rarely activated HTs are detected efficiently by our approach.The average of accuracy rate is 78% through the outlier determination algorithm and the average of accuracy rate is 87% through the density-based clustering method.