Research On Real Time Signal Interface And Processing Technology Of Embedded System

In the complex environment of signal detection,the acquired real-time signals are interspersed with strong background noise and the signal-to-noise ratio of the signals is low.Realizing the real-time processing and position parameter extraction of such weak signals has high requirements on the processing speed and storage bandwidth of the system.To address the problem that it is difficult to process weak signals in real time when the amount of detection and storage is large,this thesis investigates the real-time processing technology of multiple high speed and low signal-to-noise ratio signals,builds an FPGA processing platform,and realizes the real-time extraction of signal time delay and Doppler frequency parameters.This thesis realize the automatic amplitude and phase correction module to correct the amplitude and phase deviation of multi-channel signals and improve the signal-to-noise ratio of beam synthesized signals;store the synthesized continuous signals in DDR and read them out in sliding frames,and then carry out pulse compression processing to improve the system resolution and expand the distance search range;in response to the phenomenon of distance movement caused by the accumulation of long-time phase parameters,this thesis study the Radon-Fourier transform based on long-time phase parameter accumulation algorithm and its hardware implementation are studied to perform,distance-velocity two-dimensional search with 1200 search channels in parallel to realize information extraction;high-speed clock processing is adopted and the hardware serial structure is studied to realize the system to complete the processing of two signals in one accumulation time,in which each signal is accumulated twice serially to expand the velocity search range by 1.5times.Study the interface implementation during real-time processing,and adopt an in-band communication method to achieve high utilization of inter-board transmission channel bandwidth transmission and post-level verification;design parallel DDR storage and serial readout of high-bandwidth disorder processing results to achieve high-speed data storage and data order correction.The function correctness of each processing module of the system is verified by simulation;the board level efficiency of transmission and storage modules is verified,in which the DDR simultaneous reading and writing efficiency is the highest,supporting 76%,and the bandwidth utilization of inter board transmission channel reaches 80%;finally,an experimental platform is built to verify the system as a whole,verifying that the single channel signal search time of the system reaches ¹⁰²⁴₂₁1))second and 1800 Doppler frequency search units.