Research And Design Of Compact SM4 Encryption And Decryption Circuit Resisting Bypass Attack

As a means to ensure data security,cryptographic algorithms are widely used in security systems such as the Internet of Things.Its hardware implementation and defense against bypass attacks have been hot research topics in the field of information security.As cryptographic circuits become an important part of the domestic substitution strategy,SM4,as the first symmetric cryptographic algorithm officially announced in China,has been increasingly used in various fields of domestic information security.Because some areas such as Io T nodes and smart cards are extremely sensitive to the area overhead of cryptographic circuits,it is of great practical significance to research and design a compact SM4 encryption and decryption circuit that resists bypass attacks.The main work of this paper is to study the compact SM4 encryption and decryption circuit which is resistant to bypass attacks.For the occasions with strict area requirements,a compact design scheme based on the SM4 multiplexed T-box is proposed,focusing on the composite domain optimization method of the S-box circuit;the area overhead is optimized based on the characteristics of the parameter generation module circuit,and a multi-cycle path is used Method to reduce the critical path delay of the SM4 encryption and decryption circuit;the key expansion step of the decryption circuit is optimized by temporarily storing the reverse sequence key,and a compact SM4encryption and decryption circuit with a high throughput/gate is realized.In order to verify the ability of the compact SM4 encryption and decryption circuit to resist bypass attacks,the principles of differential fault attacks and differential power attacks were studied,and the designed circuit was verified by example attacks,which proved that it cannot resist bypass attacks.Aiming at the situation that cannot resist differential fault attacks,a compact SM4 encryption and decryption circuit design scheme based on the inverse operation comparison mechanism is proposed.The encryption and decryption circuit with fault detection capability is realized with a small resource overhead.Random single or double faults verify the effectiveness of the method.In order to achieve the purpose of defending against power consumption attacks,a T-box module was designed based on the mask and random delay technology,and a linear transformation module was designed using a random insertion pseudo-operation technology to implement a compact SM4 encryption and decryption circuit resistant to power consumption attacks;Analysis of the glitch data generated by the S-box under different inputs confirms its security against glitch attacks,and conducts DPA attacks on the design circuit.It still fails to obtain the key under the condition of 100,000 curves,which verifies that the circuit resists differential Security of power attacks.The compact SM4 encryption and decryption circuit based on Vivado software against bypass attacks is comprehensively implemented.The designed circuit achieves a 99.56 Mbps throughput rate on the Xilinx K7 series FPGA with a resource overhead of 1297 LUTs and 536 FFs.The designed circuit is synthesized,and the circuit area overhead under the SMIC 0.18?m process is 111,774?m~2,which is a 44.4%reduction compared to other papers.