Design Of Fine-grained Classification Algorithm Based On Meta-learning And FPGA Verification

Few-shot fine-grained recognition is widely used in many fields,such as bioscience and intelligent security,where there is no way to provide a large number of samples.However,the accuracy of the existing algorithm is too low to be applied,and the classified number is too small to be used,thus,it is challenging to be applied in practice.In addition,in many cases,remote computing has high cost and high requirements on the external environment;but the existing algorithms tend to ignore the application efficiency of hardware,so the circuit design has practical significance and broad development prospects.This thesis focuses on the design of hardware and software cooperation,including optimizing algorithm,FPGA design,and FPGA verification.For algorithm,an end-to-end neural network model is designed by combining meta learning with FCN network,which is used to improve the accuracy of the algorithm without additional computation.For FPGA,the computational efficiency of the neural network is improved by designing highly parallel neural network accelerators and corresponding external circuits;then it is synthesized and simulated to analyze the power consumption,area,timing and other attributes of the circuit;finally,it is verified in Miz-7035.On the Stanford Dogs dataset,for 10 classes,our proposed algorithm achieves 63.36% accuracy only with 7samples;for 5 classes,the accuracy is up to 69.35% and 76.37%.At 100 MHz,the FPGA verification platform can recognize samples with a resolution of 84 × 84,and the recognition speed can be up to 14.49 FPS.This thesis is useful for the algorithm design of AI chip and FPGA implementation of large neural network.