Research On Photometric Stereo 3D Face Reconstruction Based On FPGA

Biometrics is a research direction that has attracted people's attention in the field of machine vision,and face recognition is the current research hotspot.Affected by many factors such as facial expressions,environmental backgrounds and facial gestures,it is difficult to ensure the accuracy of the facial recognition.How to quickly and accurately reconstruct a threedimensional facial model is particularly important.Photometric stereo vision technology is a classic three-dimensional reconstruction technology in the field of machine vision.It has the advantages of non-contact and high accuracy,but also has the disadvantages of complicated equipment and poor real-time reconstruction.To this end,based on the FPGA hardware platform,this article makes an in-depth study of the basic theory of photometric stereo vision algorithm.It proposes an overall plan suitable for FPGA platform system by analyzing the parts of the algorithm that can be accelerated by hardware,combining the design requirements of the3 D face reconstruction system,and taking advantage of the collaborative development of software and hardware.The research contents are as follows:1.Build a facial image acquisition system.The system includes an OV7670 image sensor and four point light sources at different positions.It provides four grayscale images of a face under four different conditions of light sources for subsequent algorithm calculations.At the same time,the three-dimensional coordinate system of the light source and the camera is established to realize the calibration of the light source direction and the mapping of the twodimensional image to the three-dimensional coordinate system.The parameters such as the positions of the camera and the light sources are calibrated offline by Matlab,and the look-up table generated by the light source information is solidified in the ROM.In this way,the solution of the gray-scale equation is simplified.2.Optimization and improvement based on FAGA photometric stereo vision algorithm.According to the hardware characteristics of FPGA,the most time-consuming and resourceconsuming gradient field integration module is optimized.Integrating the gradient value of the gradient field integration module based on two-dimensional FFT is mainly achieved through multiplication and accumulation calculations.Due to its low algorithm complexity and large amount of computation,this method is quite suitable for taking advantage of FPGA logic circuits in hardware acceleration.The improved photometric stereo vision algorithms are all verified by Matlab simulation,and the verification results show that the algorithm functions can be realized normally.3.Design and implementation of photometric stereo vision hardware platform.The platform takes Xilinx Artix-7 series FPGA as the core computing platform and uses SRAM,RAM,ROM and FIFO to realize the storage of the original images and the cache of the intermediate data.The UART outputs the 3D reconstruction results.In order to improve realtime performance,hardware acceleration methods such as ping-pong operation and data cache are used to optimize the design.It also makes full use of the parallel structure of FPGA,which optimizes the resource utilization and improves the computation speed.Verilog HDL language is used for hardware programming,and the functional simulation of each module in the algorithm is verified on the vivado platform.The final system test shows that on the FPGA platform with a system working clock of 100 MHz,a three-dimensional face reconstruction system with a resolution of 128 × 128 face reconstruction system and a reconstruction speed of up to 60 fps is realized.The three-dimensional face reconstruction system optimizes complexity of the algorithm.Combined with the characteristics of FPGA logic parallelism,it improves the running speed of the algorithm and meets the requirements of real-time reconstruction.It has good application value and prospects in the application fields of smart home face recognition and chip prototype design analysis.