Design And Implementation Of Uplink And Downlink Data Transmission Method In Massive MIMO Systems

The 5th Generation Mobile Communication Systems(5G)New Radio standards define flexible parameter sets and frame structures,and introduce new technologies including large-scale antennas,beamforming,and new channel coding schemes.While greatly enhancing the user-centric experience of mobile Internet services,5G will fully support the object-oriented Io T business and realize the intelligent interconnection of people,objects and things.Large-scale multiple-input multiple output(MIMO)technology allocates a large-scale antenna array at the base station side to fully exploit spatial dimensional resources,which can significantly improve the transmission reliability and spectrum efficiency of communication systems.This paper is aimed at the MIMO prototype verification system under the wide broadband and large-scale antenna configuration,and for the 5G evolved massive MIMO uplink and downlink data transmission methods,the focus is on the two issues of broadband massive MIMO signal processing and LDPC encode and decode technology.On this basis,we complete the design and implementation of large-scale MIMO signal processing and variable code length and variable code rate LDPC encoder and decoder based on FPGA chip.The specific content includes:Firstly,for the 5G evolution-oriented large-scale MIMO system uplink and downlink data transmission,the scrambling,modulation,layer mapping,resource mapping,OFDM modulation and other processing procedures are reviewed.Furthermore,around the two major problems of computationally intensive MIMO signal processing and channel coding and decoding in the uplink and downlink data transmission of largescale MIMO systems,the difficulties and challenges faced in hardware implementing are analyzed.Finally,we design the system architecture and hardware composition of a large-scale MIMO prototype verification system based on FPGA computing architecture.Secondly,this paper completes the FPGA architecture design and implementation of broadband largescale MIMO signal processing including downlink precoding and uplink signal detection.During downlink transmission,the proposed implementation architecture is compatible with traditional precoding such as Matched Filter(MF),Zero Forcing(ZF),and Regularized Zero Forcing(RZF)and robust precoding based on statistical channel information and instantaneous channel information.During upstream transmission,the proposed implementation architecture is compatible with multiple detection methods including MF detection,ZF detection,Minimum Mean Square Error(MMSE)detection,and MMSE simplified algorithm based on QR decomposition.On this basis,the platform functional module division of the large-scale MIMO signal processing part of the system,the logical design and implementation of each sub-module and the corresponding fixed-point design are completed,and the FPGA chip resource consumption is given.Finally,this paper completes the design and implementation of a length & rate-variable LDPC encoder and decoder.Focusing on the problem of low resource efficiency of the traditional parallel coding and decoding structure when supporting variable code length and variable code rate LDPC codes,an implementation structure of an LDPC encoder and decoder supporting parallel processing of multiple blocks with different parameters is proposed.On this basis,strategies such as code block parallelism,code block interleaving,check matrix rearrangement,offset cyclic shift and distributed check termination are optimized.Then the module function division,module logic design,implementation and testing are completed.Performance such as FPGA chip resource consumption,throughput and bit error rate are given,which show that the proposed and designed LDPC encoder and decoder has high-speed and high-efficiency design features and can solve the problem of low resource efficiency.Finally,based on the 5G NR LDPC encoder and decoder,the configuration flow of the general QC-LDPC encoder and decoder is given.