Design And FPGA Verification Of Behavior Recognition Algorithm Based On Attention Mechanism

With the increasing demand for smart cities and smart security,smart video technology is developed,and behavior recognition technology is indispensable in smart video systems.The current behavior recognition algorithm is difficult to achieve a high recognition rate under the condition of lower algorithm complexity.So,the behavior recognition algorithm with low calculation amount and high accuracy is proposed in this thesis,and the algorithm hardware verification is completed based on FPGA.After comparing and analyzing the performance of different algorithm structures,the Res Net-50 plus LSTM algorithm structure with low computational complexity and relatively high accuracy is selected,and the recognition accuracy rate is 79.10%.In order to further improve the accuracy rate,the negative feedback attention mechanism is introduced into the algorithm structure of Res Net-50 plus LSTM.A single-layer attention and a multi-layer attention scheme are designed,and the loss function is reconstructed.The accuracy rate of the single-layer attention scheme is 85.79% when the overall calculation amount is increased by a small amount.Finally,in order to reduce the amount of hardware operations and weight storage space,the fixed-point quantization method is proposed in this thesis.The experimental results show that the accuracy rate is 85.75% when the parameter amount drops by75%.In order to verify the accuracy and speed of the algorithm in actual application deployment,the verification of the algorithm hardware acceleration scheme based on the FPGA platform is completed.From the consideration of data multiplexing and parallel computing,a FPGA-based neural network accelerator with dual parallelism on the input and output channels is designed and implemented.When the operating frequency is 100 MHz,the behavior recognition accuracy rate is 84.8%,and the recognition speed is 65f/s.