Design And FPGA Implementation Of Unsupervised Depth Estimation

In recent years,unsupervised depth estimation has become popular research directions in the field of computer vision,and is widely used in the fields of 3D reconstruction,semantic segmentation,SLAM and so on.Considering the practical application of algorithms,FPGA is able to take into account the calculation through targeted hardware design performance and power consumption,realize the accelerated design of the algorithm on the hardware platform.Under this background,this thesis takes unsupervised depth estimation as the starting point to realize the hardware accelerated design.Firstly,this thesis selects the hardware-friendly Goard's algorithm as the benchmark.In order to match the hardware,the amount of calculation and parameters of the model must be reduced.In this regard,this thesis proposes a multi-scale structural similarity index in the design of the loss function to fully describe the difference between images.Restructure the model structure of the benchmark,and use fixed-point quantization.For the reconstructed model,this thesis designs a dynamic learning rate and proposes an iterative training model retraining method.In the end,based on the Goard's algorithm,this thesis obtained a high-precision and compact algorithm,the parameter amount was reduced to one-fifteenth of the benchmark,which is 5.3MB,and the amount of calculation is reduced to one-third of the benchmark,which is 5.6GOPs,the RMSE in the KITTI 2015 dataset is 4.270,which is reduced by 4.5% compared to the benchmark.Considering the structure of the algorithm model and the resource limitations of the hardware platform,this thesis co-designs the two parts of the Processing System and Programmable Logic in the FPGA,uses the dataflow of feature map stationary,and designs customized dataflow.At the same time,this thesis proposes a design method of fusion upsampling calculation is proposed for the deconvolution operation,and a design method of jumping sliding window is proposed for the maximum pooling operation.The experimental results show that the running time of the operations are reduced by 68.9% and 34.8%.Finally,this thesis completes the accelerated design and system verification on the MZ702 N platform.The efficiency is 6.13 GOPS,the power is 2.512 W,the energy efficiency is 2.44GOPS/W,and the performance is 1.09 fps.This thesis completes the research of unsupervised depth estimation and the hardware accelerated design on FPGA platform,which provides a reliable reference solution for subsequent related research work.