Implementation And Acceleration Of Scalable Tracking Algorithm

Object tracking is an important part of computer vision,and is widely used in areas such as autonomous driving and traffic control.The tracking algorithm has been greatly developed,but at the same time it is also facing many challenges.It is more and more difficult for traditional tracking algorithms to meet the requirements.With the popularization of machine learning,discrimination algorithms have received more and more attention and become the mainstream tracking method.Among them,correlation filtering algorithms have become research hotspots in recent years due to their advantages in speed and performance.The traditional correlation filter algorithm uses a fixed target window size,which cannot adapt to the scale.As algorithms become more and more complex,scale estimation becomes the standard for most tracking algorithms.In the framework of correlation filter,the DSST algorithm proposes a scale filter,which can effectively track scale changes.However,the addition of scale reduces the speed of correlation filter algorithm and cannot run in real time on embedded devices.So this paper uses FPGA to accelerate the scale filter and implement a complete tracking system.The main research work includes:(1)Optimize the scale filter to better run on hardware.The HMG feature is proposed,which can describe the scale graph in a small number of dimensions.HMG does not need to calculate the direction and modulus of the gradient,and can only complete the feature statistics based on the gradient component,which greatly saves hardware resources and speeds up the running speed of the algorithm.(2)Based on optimized algorithms,scale filters are implemented on FPGA.The pipeline structure is used to implement the modules of gradient calculation,feature statistics,cosine filtering and DFT.Among them,adopting SDFT to realize the DFT.And optimize the structure according to the CCS structure of the spectrum,which can save a lot of hardware resources.(3)According to the "ARM + FPGA" architecture,the system is designed for software and hardware.The scale filter is hardware accelerated by FPGA,and ARM is responsible for flow control and floating point processing.Through flexible hardware and software division,the system's computing efficiency and real-time performance are improved.In addition,the upper computer program is designed on the PC to test and demonstrate the system.This article selects OTB to test the system,and finally achieves a speed increase of about 2 times in terms of the performance accuracy close to the original algorithm.