The Design Of Real-time Schedulable DMA On DSP Chip Based On AXI4.0 Bus Protocol

With the rapid development of digital signal processing technology,people's demand for high-performance DSP is increasing,and multifunctional DSP supporting high-speed data transmission has become the mainstream trend.Direct Memory Access(Direct Memory Access),as a bridge between DSP internal storage and external devices,plays a crucial role in the design of modern DSP systems.At present most domestic product producers adopt traditional DMA design,and the traditional mode of DMA design based on register waiting transmission mode,the way in the new high-priority transmission transaction to temporarily unable to make real-time response,increased external devices and the CPU waiting delay,lack of certain schedulable DMA transfer process,and the transmission speed is slow,the channel number is less.Therefore,it is necessary to design a DMA controller with fast transmission speed and real-time schedulability to meet the application demand of data transmission in high-performance DSP system.This paper aimed at the traditional DMA in scheduling of work in the sex is not high question,through the analysis of the traditional internal DMA channel architecture,designed a priority can be configured polling arbitrator,and thereby puts forward an internal channel,the mechanism of interrupt jump to high-priority transmission transaction jump to realize zero wait,effectively reduce the external devices and the CPU waiting delay to improve the real-time scheduling can be in the process of transmission.Secondly,the transmission of register mode and descriptor mode is compatible and optimized in the design,so that the transmission process can realize arbitrary switching between the automatic buffering mode and the chain transmission mode,which improves the transmission speed and reduces the hardware consumption.Finally,the signal and characteristics of DMA controller are analyzed,and the configurable polling arbitration module,register read-write module,schedulable transmission control module and other functional modules are designed,and a real-time schedulable DMA controller is designed based on AXI4.0 bus protocol,which is suitable for modern DSP.This design uses verilog HDL language to complete the RTL level design from the top down,and through the establishment of UVM verification platform for its verification and analysis,to achieve 100% functional coverage.FPGA prototype verification was completed on the development board of EP4CE115F23I7 N of Quartus platform,and the overall layout design and back-end timing analysis were finally completed based on the TSMC90 nm CMOS process library environment.Compared with the traditional DMA controller,this design can flexibly schedule DMA work in the DSP system environment,and can respond to the high-priority equipment in real time and the response is no more than 24 ns,so that the DMA controller has a strong real-time schedulability.In addition,the design has 14 priority configurable channels,data throughput up to 6.9Gbps,on the basis of meeting the requirements of multichannel has a higher transmission rate.