Design Of Configurable Chip With Low Storage Occupation For Consumables Safety Certification Management

With the development of the integrated circuit industry and its widespread use in common consumables,the consumable management and safety issues that follow have become increasingly prominent.Consumable management chips are often subject to malicious cracking attacks,the main method of which is power consumption analysis attacks.Currently,masking technology is the mainstream method for defense power analysis,but traditional Boolean masking cannot be completely random if it does not occupy a large amount of storage resources.Moreover,the consumable chips using these solutions cannot defend against the problem of chip reverse engineering attacking.At the same time,advanced consumable chips have high requirements for versatility and flexibility in use.Traditional solutions are usually limited by area and can only fix the chip function,so they cannot be configured according to actual needs.Repeated design increases development costs and application complexity.Therefore,it is necessary to design a low-memory fully random mask configurable consumable management chip to meet the requirements of the area cost,security,versatility and flexibility of the chip in the use of consumables.This article first analyzes and compares the current mainstream masking technology solutions,combined with the application requirements of advanced consumer chips,summarizes the advantages of using Boolean masking technology.In order to solve the problem that the authentication system using a Boolean mask requires a lot of storage resources.This paper proposes a scheme to alternately use two Boolean masks in an algorithm process.This scheme effectively reduces the number of look-up tables required during the AES algorithm and thus reduces the storage space occupation.However,the above scheme will input a fixed mask into the lookup table,so it is vulnerable to attacks.This paper also proposes a randomized algorithm flow scheme that randomly controls the operation sequence of the AES algorithm through true random numbers and disrupts the power consumption information when the data enters the look-up table.Combined with clock disturbing technology to cover the power consumption information of weak points,it effectively improves the design's ability to resist power analysis.Finally,the traditional consumable chip has the problems of single communication method and fixed function,resulting in a wide variety of similar products.This article considers the application scenarios and needs of various consumables management chips,and designs a consumables management chip that can initialize the built-in non-volatile memory through the serial port and easily configure the chip functions.This design satisfies the requirements of the versatility and flexibility of the consumable management chip,greatly reducing the cost and development cycle of repeated design.This article uses Verilog HDL language for RTL-level hardware implementation,and uses VCS to complete functional simulation.Then FPGA verification is performed based on the Quartus II,and the random number generated by the RRNG meets the NIST random number test standard.Finally,HH Grace's 0.13?m process is used for logic synthesis and layout to obtain the overall layout,and timing analysis,power consumption analysis and post-simulation of the netlist.The chip area is 2.25mm~2.The average power consumption is 0.38m W during authentication,0.34m W for read and write after authentication.The chip can be configured to support standard IIC contactless communication mode or ISO 14443 Type B contactless communication mode through a dedicated programming circuit.You can also configure whether to use SRAM cache,wireless mode modulation index,system clock speed and LDO output voltage,etc.