Audio-application ?-? Modulator Based On Time Division Multiplexing ASAR ADC

As the important interface device,ADC connects the analog signal and digital signal and is applied to radar systems,optic electric interfaces,sensors,audio and video applications.With the development of Internet of Things and portable sets,high-performance ADCs are significantly required.In these ADCs,high-resolution discrete-time?-?ADC is highly fit for audio applications.This dissertation presents a?-?modulator based on time division multiplexing ASAR ADC(Asynchronous Successive Approximation Register Analog-to-Digital Converter).The ASAR ADC performs the coarse conversion and the?-?modulator implements the fine conversion.Meantime,by time division multiplexing operation,this ASAR ADC is also used as the quantizer of the modulator loop and a compact modulator is implemented.The proposed dynamic feedback DAC decreases the thermal noise and power consumption further.The main content of the dissertation includes:(1)System design:A proposed structure is presented and based on ASAR ADC and three-order?-?modulator which consists of Silva-Steensgaard structure and Noise-Couple.In order to improve the maximal SNR,the low-power and compact ASAR ADC as a Sub-ADC performs the coarse conversion.This ASAR ADC also implements the multi-bits quantization to decrease the integrator's output amplitude and improve loop stability.(2)Circuit implementations:The proposed time division multiplexing circuit implements the compact circuit by performing the coarse conversion and multi-bits quantization with one ASAR ADC.And it is convenient to extract the residue voltage and to finish the feedforward and Noise-Couple by using the switched capacitor array of ASAR ADC.Then this modulator employs the proposed dynamic feedback DAC circuit to reduce the thermal noise and power consumption.(3)Circuit design:In order to improve SNDR,sampling switches are implemented by bootstrapped switches.And the modulator adopts DEM(Dynamic Element Matching)to improve the multi-bits DAC's linearity.The Chopping circuit is implemented to reduce the flicker noise.(4)In this modulator,coarse conversion and multi-bits quantization are analyzed.Based on the proposed structure and circuit implementations,this thesis analyzes nonideal effects and build models to optimize parameters for high energy-efficiency.The modulator prototype is designed in TSMC 0.18mm 1P6M process and 1.8V power supply with layout design and post-simulation.And this modulator achieves 103.9dB SNDR and consumes 1.317m W in a 20k Hz bandwidth and a 4MHz sample frequency while occupying 0.3078mm~2.This results in a SNDR figure of merit(FoMSNDR)of 175.71dB.