Circuit Design And FPGA Verification Of VGG16 Con Volutional Neural Network

In recent years,recognition methods based on convolutional neural networks have achieved great success in a large number of applications,thanks to the rapid increase in computing power and it has become one of the most powerful and widely used technologies in computer vision.Based on the great potential and versatility of the VGG16 convolutional neural network,this article performs hardware acceleration calculations on it and reduces its power consumption without affecting its accuracy.FPGA is one of the most promising platforms for accelerating CNN,but its limited bandwidth and on-chip memory limit the performance of FPGA accelerators.This article has designed and implemented a hardware accelerator for convolutional neural networks.The accelerator is based on FPGA and is completed by the cooperation of hardware and software.which is used FPGA and ARM computing framework.The system performs forward inference on the CNN model in terms of hardware,and completes the data transmission and control of the system in terms of software.This paper started with an in-depth analysis of the VGG16 model.The focus of the convolutional layer is the calculation,and the focus of the fully connected layer is memory usage.To improve bandwidth and resource utilization,a dynamic precision data quantization method and a convolutional design that are effective for all layer types in CNN are proposed.The results show that when 8/4-bit quantization is used,the data quantization process of the VGG16 model will only introduce a 0.4% loss of accuracy.In hardware design,the accelerator is divided into several sub-modules to design using a top-down design method.The circuit design of multiple modules including the convolutional layer module CNN,pooling layer module POOL,AXI interface module and cache area module have been completed.The convolutional neural network accelerator implements the forward inference of the VGG16 model and uses a pipeline structure to improve the overall data throughput for each layer of the accelerator.Multiplying accumulators and input and output buffers between each layer reduce resource consumption through multiplexing.In terms of software,this paper designs data exchange logic and control interaction between ARM CPU and CNN accelerator.Combining hardware and software design,the IMAGENET data set has been successfully classified and identified.to Compared with the software implementation,it has a good classification result.