Design And Verification Of SNC For GPDSP With Super Million-Terafion Computing Capability

With the development of semiconductor technology,many-core processors have been widely used in the field of high-performance computing.The new-generation GPDSP processor is a high-performance,high-bandwidth,low-latency,multi-core computing processor with high-performance,high-bandwidth,and low-latency developed by the National Defense Science and Technology University in response to higher demands.However,with the increase in the number of cores in GPDSP,the communication network between the DSP core and the core becomes more and more complex,making the transmission line area overhead of the DSP core and core become larger,the transmission line delay becomes longer,and the transmission bandwidth requirements become higher.As for the cost,delay,performance and power consumption that affect the entire GPDSP project.In order to further optimize the communication network between multiple cores and off-core,a super-node architecture is adopted to realize communication between multiple cores and off-core.The purpose of this topic is to design a supernode controller in the GPDSP with a processing capacity of more than one trillion trillion times,so that the supernode controller can satisfy multiple processing while optimizing the communication network of many DSP cores and on-chip buses.Unit data arbitration,data distribution,broadcast operations,burst operations,data movement and AXIization requirements.In GPDSP,a supernode is composed of four DSP cores and a fence synchronization unit.A supernode controller is a transit control center for data interaction between multiple DSP cores in the supernode and off-core.It is divided into data channels and configuration channels.The design work of this project is divided into four parts,namely the design of the supernode controller data path,the verification of the supernode controller data path,the design of the supernode controller configuration path and the verification of the supernode controller configuration path.The design of data path and configuration path is based on AXI bus protocol.The data channel is composed of four channels: read address channel,read data channel,write channel,and write response channel.It mainly implements data data interaction between the four DSP cores in the supernode and the on-chip bus;the configuration channel is read and written by Jtagc.The write confirmation channel,the L1 C read-write configuration channel,the L1 C read data channel,and the L1 C write confirmation channel are mainly used to realize the transmission of the configuration signal of the CPU,Jtag or peripheral configuration module to the DSP core.The supernode controller uses a separate data channel,uses a two-way VALID and READY handshake mechanism,and also supports unaligned data transmission,burst data transmission,broadcast,and out-of-order transactions.The super node controller designed in this subject has the following innovations:(1)Super node controller is compatible with AXI bus,so it has greater flexibility and portability;(2)The broadcast unit is added in the design of the super node controller,thereby reducing the bandwidth pressure of the on-chip network;(3)A Transfer unit was added to the design of the Super Node controller,thereby reducing the bandwidth pressure of the DSP core;(4)The design of this super node controller is programmer friendly,it can solve the problem of misaligned memory access,especially the transmission mode.During the verification process of the super node controller,a function verification platform for the Data network and the configuration network is set up to perform the function verification.The verification platform is composed of modules such as a super node controller module,a gold model,an incentive generation module,and a Compare module.According to the test plan and test cases,the incentive is loaded into the verification platform,the response is obtained,and the response is confirmed to meet the expected functional goals.All functions of the Super Node Controller are implemented correctly.After the functional verification is completed,DC synthesis is performed to obtain the timing report,area report and power consumption report of the super node controller to verify the feasibility and correctness of the performance,area and power consumption of the super node controller.The comprehensive DC results show that the critical path delay of the Super Node Controller is 0.36 ns,and the operating frequency of the SNC can reach 2.85 GHz.The area overhead of the SNC is 29927.09um2,of which the area overhead of the Data network is27291.74?m2,accounting for 91.19% of the total area;the area overhead of configuring the network is 2635.35um2,accounting for 8.81% of the total area.The total power consumption of the SNC is 53.9710 m W,of which the Data network power consumption is46.9752 m W,accounting for 87.04% of the total power consumption;the power consumption of the configured network is 6.9958 m W,accounting for 12.96% of the total power consumption.The verification and comprehensive results show that the SNC can achieve the functional goals on the design document,the operating frequency is above2.0GHz,the area overhead and the total power consumption are in line with expectations,so the SNC design meets the design requirements.