Design And Implementation Of High-speed Chaotic Encryption System Based On FPGA

The semiconductor industry still follows the Moore's Law and develops rapidly,correspondingly,communication technology has also made great progress.A huge amount of information is stored and interacted on the Internet all the time.However,in recent years,information leakage has frequently appeared,and the importance of information security has become increasingly prominent.Chaotic system,with its unique dynamic behavioral characteristics,is consistent with encryption system's design principles of obfuscation and diffusion,thus plays a brilliant role in the field of information security.However,when the chaotic system existing in the real number domain is implemented by digital circuit,it is found that chaotic system will eventually collapse into the finite domain,and appear the degenerate phenomena such as short period and multi-period in dynamic behavior characteristics,affecting information security.How to resist the degradation of dynamic behavior characteristics of digital chaotic system is the key to applying chaos to information security.Taking the proposed digitalized anti-degenerate chaotic system as the core of key stream generation,this paper constructs a high-speed encryption system based on chaos theory.What's more,the hardware implementation and board level verification are completed by FPGA.Combined with the strong bit processing ability of programmable hardware circuit,a pseudo-random sequence periodic orbitals detection algorithm based on FPGA is proposed to solve the degradation problem of dynamic behavior characteristics.By adopting multi-path parallel operation,the rapid response ability to periodic phenomena is improved.Then,for the anti-degradation problem,based on the proposed algorithm,combining with the idea of disturbance,a method of resisting chaotic dynamical degradation based on deterministic periodic jump is proposed.Taking the proposed anti-degradation method as the core,using the stream management mode in FPGA,a simple encryption system is designed.In addition,its high-speed hardware is realized by various accelerating operations.What's more,the corresponding hardware implementation and board level verification are carried out.As the simulation results shown,the proposed algorithm from the perspective of the hardware can quickly detect whether there is a period of the digital chaotic system.What's more,the period length and all the periodic states are given.The corresponding anti-degradation method can quickly jump out of the periodic loop to traverse the state space,and the anti-degradation effect is obvious.Furthermore,the speed of encryption system is up to 454.5 MHz after acceleration.Moreover,its versatility and feasibility is verified by corresponding board level test.