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Hardware Acceleration Of The Genomic Sequence Alignment Algorithm Minimap2

Posted on:2022-09-16Degree:MasterType:Thesis
Country:ChinaCandidate:J ChengFull Text:PDF
GTID:2504306572477744Subject:Information and Communication Engineering
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With the rapid development of the DNA sequencing technology,the third-generation sequencing,which produces ultra-long reads,is becoming more and more popular around the world.At the same time,the explosion of sequencing data emerges due to the cost reduction and market expansion,bringing great challenges to the genome analysis.Sequence alignment is a fundamental but time-consuming task in genomics pipelines.Among kinds of sequence alignment algorithms developed for long reads,Minimap2 has been widely used and recognized in the field of bioinformatics because of its high speed and accuracy.Nevertheless,fast sequence alignment is bottlenecked by the computational power of existing systems when processing huge quantities of sequencing data.Hence,acceleration of Minimap2 algorithm is of great significance.Based on the research and profiling results of Minimap2,this paper proposes to accelerate the extension step which is time-consuming and computationally intensive on hardware platform for the first time.In addition,a systolic array architecture is proposed due to the independence between the anti-diagonal data and recurrence relation between the diagonal data in scoring matrix.Furthermore,the accelerator achieves task parallelism by processing multiple data packets in parallel.When designing the accelerator,this paper proposes to several optimization schemes.Firstly,using 2bit data recording the way of traceback while calculating the scoring matrix to optimize the hardware implementation of the traceback process.Secondly,a new PE cascading method which is called CVLL is proposed to decrease the unnecessary latency and wasting resources on FPGA.Finally,the pipelining technique and multi-channel technique are applied to the hardware implementation to further improve the accelerator performance.In the verification process,a UVM-based verification plan is proposed to solve the inconsistency between the simulation and the experiment results.After all the functional coverage points are covered,we use sequencing data with different read lengths to test the performance of the accelerator.Our experimental study shows that the read length,PE length,and the number of channels have substantial impact on performance.Our kernel implementation is up to 130 x faster,compared to the software-only execution.In conclusion,our hardware accelerator significantly improves the performance of Minimap2 Algorithm,which can provide guideline for the overall acceleration of the genomics data processing and the hardware implementation on the application-specific integrated circuit in the context of the growing gap between the speed of genomics data generation and data analysis.
Keywords/Search Tags:Sequence alignment, Minimap2, FPGA, Hardware acceleration
PDF Full Text Request
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