The Research Of High Frequency And Low Noise Clock Source Based On CMOS Technology

With the development of high-speed communication and high-speed ADC,the performance requirement of clock source becomes more and more important.Clock source is developing towards low phase noise,low jitter and low power consumption.Phase-Locked loop is the most commonly used clock source structure,because it can suppress low-frequency noise and long-term jitter of oscillator,which can produce a purer clock signal.This project aims to realize a high-frequency and low-noise phase-locked loop to generate high-quality clock signal chip and complete its circuit principle analysis,circuit design and tape-out verification.Cadence Virtuoso platform is used in this dissertation to design a high-performance VCO with the TSMC 180 nm CMOS process.The VCO utilizes the transformer feedback and successfully embeds the common mode resonance technology into the transformer,which can save an inductor area.Moreover,the embedded solution avoids the problem of frequency instability caused by other embedded solutions.The chip has been taped out,tested and verified.With the power supply voltage of 700 m V,the power consumption is 6m W,and its output frequency range is 5.55-6.9GHz.The optimization of its common mode resonance to noise can be verified through simulation and testing.At the output center frequency of 6.16 GHz,when tuned it to this common-mode resonant frequency,the phase noise performance can be reached-123.7d Bc@1M and-135.2d Bc@3M,and the FOM values can be calculated as-191.5d B@1M and-193.45 d B@3M.The VCO can achieve high performance.On the basis of the above VCO innovation,under the TSMC 65 nm CMOS process node,the oscillation frequency is increased,and the magnetic coupling is used to further expand into a dual-core VCO structure.The lower phase noise of the VCO is achieved through simulation verification.A sub-sampling phase-locked loop（SSPLL）is designed and fabricated based on the dual-core VCO.The theoretical analysis of the SSPLL bandwidth is complted and circuit blocks of the SSPLL is designed to achieve the best performance optimization.The layout of the SSPLL is finally completed,and post-layout simulation shows that the output frequency of the phase-locked loop is8.4-10.2GHz;the integral jitter of 1k～100MHz is 21.52 fs.The overall power consumption is 47.69 m W and its FOM value can be calculated as-256.6d B.