Data Preprocessing Design Of Harmonic Analysis Module In Power Analyzer

As an important measuring instrument in power quality analysis,the power analyzer can realize a variety of functions such as waveform display,power parameter calculation and harmonic analysis,which provide a visual and quantifiable evaluation method for the quality analysis of the power system.In order to obtain higher refresh rates and calculation accuracy,it will be of great significance to improve its real-time processing performance.This thesis takes the power analyzer as the research object,focusing on the implementation method of the harmonic analysis function.It changes the traditional processing method which takes CPU as the core of data operation,and takes the field programmable gate array（FPGA）as the core of data collection,by achieving a large number of data preprocessing tasks in harmonic analysis into the FPGA.This method has a significant effect on improving the operation accuracy and speed of harmonic analysis.It can effectively use the operation resources of FPGA,to achieve the purpose of hardware acceleration of key algorithms.The research content of this thesis mainly includes the following aspects:1.In order to meet the requirements of multi-channel data processing and display,it is usually necessary to consider the phase difference of the signal itself.To reduce the phase difference,it is necessary to find a adjustment method with higher applicability.Many researchers have proposed an interpolation fitting algorithm to recover different phase information.The key of this method is to find a high-precision,low-computational implementation to achieve high-precision phase adjustment function.Based on FIR interpolation filter,this thesis presents a fast convolution architecture based on multiphase structure,which can improve the accuracy of phase adjustment and reduce the amount of computation of high-order FIR filters.2.Due to the limitation of sampling rate and number of sampling points,when analysis the spectrum of the harmonic signals with complex frequency components,it will produce a certain overlapping effect on the frequency components of effective bandwidth range by the high and low frequency components.Bandwidth limiter is usually needed to remove the invalid frequency components.Based on IIR digital filter,this thesis achieves bandwidth limitation with low cost,multi-function and variable cutoff frequency through variable-speed multistage cascade architecture.3.Spectrum analysis is a critical process in harmonic analysis.It is difficult to achieve the requirements of high-frequency and high-resolution harmonic analysis simultaneously when fewer operating points are used.Based on the premise of not reducing the number of harmonic analyses,the method of increasing the number of operation points is usually used to improve the frequency resolution,but the problem of large amount of computation caused by large number of points calculations is the bottleneck that traditional instruments are difficult to break through.Based on the traditional base two butterfly algorithm,this thesis presents a reconfigurable circuit operation architecture for pipelining parallelism,which achieves fast operation of largepoint FFT by replacing the traditional software operation with the use of FPGA.According to the relevant test results,it shows that the phase adjustment function with step accuracy less than 3ns can be realized in this paper;In the digital filter,the relative error at-3d B is less than 0.1%,and the maximum attenuation of passband is less than 0.01%;The calculation rate requirement that the single FFT operation time is less than 1ms in 3+3+1 phase system is implemented.