| Through the construction of genetic cell engineering biosensor by means of synthetic biology,interconnect with integrated circuits,which is of great scientific significance and transformation application prospect for the diagnosis and treatment of metabolic diseases.For the power management system in the chip related to genetic cell engineering biosensor,it needs to have the characteristics of low power consumption,so its design is very challenging.Based on SMIC 40nm CMOS technology,a low power consumption power management system for low-power biological weak optical signal detection So C is designed in this paper.The core achievement of this paper is:1.The functional requirements of So C for its power management system are detected by low-power biological weak optical signal,and the architecture and module composition of the power management system are formulated:the power management system consists of one LDO with off chip capacitance,three LDOs without off chip capacitance,one voltage reference that can output 670m V and 1.25V,one current reference that can output 10n A and 100n A,and one current reference that can output500n A and 1μA.Through the static power requirements of low-power SOC for the power management system,the static current of each module in the power management system is formulated.2.According to the requirements of different LDOs（low dropout linear regulator）for static current and transient response speed,four LDOs with different structures are designed:A 10μF off-chip pole compensation LDO with 3.3V input voltage,2.5V output voltage and 3.97μA static current is designed,and a voltage buffer is designed between the error amplifier and the power transistor to improve the driving capacity of the error amplifier and ensure the stability of LDO under heavy load;An ultra-low power LDO with 2.5V input voltage,1.1V output voltage and 51n A static current is designed,a dynamic bias circuit is designed for the error amplifier to improve the transient response of the LDO as much as possible under the guarantee of ultra-low static current;An LDO with input voltage of 2.5V,output 1.25V,static current of1.92μA and maximum driving load of 10m A is designed,an error amplifier with a common gate input stage and a push-pull output stage is designed for the LDO to improve its transient response,on this basis,a dynamic bias circuit is added to detect the output voltage through capacitive coupling to form a dynamic current,so as to obtain a faster transient response at a lower static current;An LDO with input voltage of 2.5V,output voltage of 2V and static current of 30.25μA at no load is designed.The LDO is used to improve the slew rate of the error amplifier and bandwidth at heavy load using adaptive bias technology.In order to compensate the stability of LDO,a zero pole tracking circuit is designed to ensure its stability during heavy load.3.For the designed LDOs with four different structures,they have different requirements for reference voltage and bias current.Based on this,an extremely low static power consumption voltage reference with static current of only 0.23n A～1.12n A and low temperature coefficient output voltage based on the difference between negative threshold voltage of Depletion MOS transistor and the high threshold voltage of thick oxide transistor is designed,The voltage reference realizes two different reference voltages of 670m V and 1.25V by setting different numbers of PMOS transistor to provide them to their required LDOs respectively,and adopts the method of digital control bits to reduce the fluctuation of voltage reference caused by different process corners;Based on the traditional sub threshold current reference combining CMOS and on-chip high resistance,a static current of 57.6n A is designed.The NMOS transistor working in the linear region is used to replace the on-chip high resistance,which reduces the layout area,realizes the all CMOS low-power current reference,and adopts the starting circuit composed of only two PMOS transistors to separate it from the degenerate point after power on;A static current of 16.6μA is designed.The operational amplifier is removed,so as to reduce the static power consumption,An auxiliary branch is designed to eliminate the Vds difference of transistors in the current mirror of the core circuit,the accuracy of the output voltage can be improved,and reduce the temperature coefficient of the output voltage.4.The layout of each module of the power management system is designed and embedded into the overall layout of low power biological weak optical signal detection So C.Firstly,the layout of each module is extracted parasitically by Calibre,and the LDO,voltage reference and current reference are simulated after.Then,through parasitic extraction of the overall layout of low-power biological weak optical signal detection So C,Monte Carlo simulation is carried out on the output voltage of LDO in the overall power management system to verify the accuracy of each LDO output voltage:The average output voltage of the four LDO Monte Carlo simulation is:2.51146V,1.26079V,2.04408V,1.15364V,the standard deviation is 120.47m V,59.481m V,94.9069 m V,46.4177 m V;Then the static current of each LDO,current reference and voltage reference is compared with the static current budget of the system,which proves that the power consumption of the low-power power management system designed in this paper meets the performance indicators:The static currents of the four LDOs are 3.97μA,51.367n A,1.92μA,30.25μA,respectively.The static currents of the voltage reference are 0.23～1.12 n A,and the static currents of the two current reference are 57.6n A and 16.6μA,respectively. |
