System And Circuit Design Of An Inference Machine Based On 1T1C DRAM Cell

Because of its brain-like operation mode,neural network is able to deal with a large number of nonlinear problems,and thus has become the main algorithm architecture in modern artificial intelligence and machine learning.With the increasing complexity of specific application scenarios,the neural network system is becoming larger and larger,and the data and weight to be read by a single operation are constantly increasing.The data bandwidth of memory limits the continuous growth of the overall speed of the neural network system.Inmemory computing breaks the Von Neumann architecture and places the weight of neural network in all kinds of memory,including DRAM.By analyzing the data storage and transmission characteristics of the memory,the weight of neural network is calculated directly in the memory,without the need for weight transmission,which reduces the bandwidth requirement of overall data.Starting from the traditional DRAM unit,this paper studies the time domain characteristics of charging and discharging of DRAM unit by combining simulation and analytical calculation.It is found that when the MOSFET in DRAM works in the unsaturated region,the capacitance is related to the input voltage and charging time at the same time,which meets the requirement that the result should be related to the two variables in one multiplication calculation.Considering about this characteristic,a multiplier structure with analog voltage and different pulse width signal which turns DRAM on and off as two input signals,and the voltage value of capacitor after charging and discharging as the calculation result is determined.The relationship between capacitor voltage and the input voltage is analyzed.In order to expand the input voltage range and guarantee the MOSFET in unsaturated zone,based on conventional DRAM unit,this paper proposed a PMOS and NMOS parallel DRAM circuit structure,when the input voltage is lower than 0.9 V,when the input voltage is higher than 0.9 V,charging current flows from NMOS to capacitor,results in expand the input voltage range of the multiplier to 0 ～ 1.8 V,and the input voltage and capacitance voltage has a good linearity.At the same time,the paper analyzes the relationship between the capacitor voltage and the charge and discharge time,found that the capacitor voltage and charging time is in tanh function approximately,convert the pulse width parameter,the converted parameters and multiplication result has a good linearity,which met the multiplication results at the same time with two variables into linear function relation.Considering that the pulse width is never negative,in order to realize the multiplication of negative numbers,the rule of multiplication is analyzed,and the solution of changing the mathematical symbol of the input voltage is proposed when the pulse width should be negative but the actual pulse width signal is positive.The circuit and algorithm of DRAM multiplier with sign based on analog signal input are designed.A 4×5×3 neural network inference system was constructed by using the designed multiplier and activation function circuit.The classification problem of iris datasets was selected to train the inference system at the software level.The stochastic gradient descent method and cross entropy loss function were used to obtain 97.3% classification accuracy after 1000 training rounds.After the corresponding weights are transformed into electrical signals by the conversion algorithm defined in this paper,and iris datasets are transformed into analog voltage value,they are injected into the hardware neural network inference system as the stimulus and control signals,and the simulation results of the hardware neural network inference system is carried out.The classification accuracy of the hardware system is 97.3% as the same as that of the software at the TT process corner and 27℃.By studying the time domain characteristics of DRAM capacitor,a reasonable multiplication circuit and the specific timing sequence of multiplication algorithm is proposed.By comparing the accuracy of hardware neural network inference machine system based on this DRAM multiplier to solve iris classification problem with software,validated the availability of the DRAM multiplier-built hardware inference system and equivalence between ideal neural network algorithm,which provides a new design idea of neural network based on DRAM in-memory processing.