Design Of High Precision Delta Sigma ADC In BMS Chip

The battery management system chip is the key to ensuring the safety and work efficiency of the power battery system.High-precision battery parameter monitoring is the basis of the BMS chip,which completes the monitoring of the voltage,current and temperature of each battery.The monitoring results are used to estimate the battery status to prevent the battery from working outside the safe operating range,while ensuring different batteries ensure are in a balanced state.Since the various parameters of the battery are low-frequency signals close to DC,the Delta Sigma ADC,which exchanges speed for conversion accuracy,with its advantages such as high accuracy and low power consumption,has become the best choice for monitoring battery parameter analog-to-digital conversion in BMS chips.This paper has carried out the research and design of the low-power,high-precision Delta Sigma ADC applied to BMS chip,comprehensively considering factors such as speed,power consumption and accuracy,the structure of the fourth-order feedforward modulator with unit quantization and oversampling ratio of 128 and the structure of the5-level CIC digital decimation filter are determined,and the system-level model Stability and performance are analyzed.The Delta Sigma modulator is divided into modules such as fully differential operational amplifier,integrator and quantizer,which are designed and realized by switched capacitor circuit,and amplifier chopping technology and sampling capacitor chopping technology are added to the first-stage integrator to reduce the impact of low-frequency noise and DC offset.The RTL design of CIC filter is completed using Verilog language,and the decimation rate of the CIC filter can be configured to achieve different output data rates of 7.8125Hz-1000Hz,and the default decimation rate is 256,the corresponding output data rate is 1000Hz.The overall signal-to-noise distortion ratio of the ADC circuit level is 111.2d B,and the effective number of bits is 18.18bit.Using tsmc 0.18μm CMOS process,the layout design of the Delta Sigma modulator is completed in a fully customized manner,and the layout of the CIC filter is completed by automatic placement and routing,and the overall ADC layout consumes an area of1.89mm²,and the overall post-simulation SFDR is 108.3d B,THD is-108.3d B,SNR is116.9d B,SNDR is 107.7d B,and ENOB is 17.60bit.Using the same test analysis method as TI chip ADS1246,that is,testing the chip by short-circuiting the input to measure the noise.When the power supply voltage is 5V and the data rate is 1000Hz,the noise of the ADC is 2.23μV_RMS,the ENOB is 21.10bit,and when the data rate is 7.8125Hz,the noise of the ADC is 0.16μV_RMS,the ENOB is 24.90bit,and the analog modulator circuit consumes approximately 220μA of current,which meets the design expectations.