Font Size: a A A

Design And Verification Of 1553B Bus Interface Logic

Posted on:2022-10-23Degree:MasterType:Thesis
Country:ChinaCandidate:S ChenFull Text:PDF
GTID:2492306572450254Subject:Instrument Science and Technology
Abstract/Summary:PDF Full Text Request
The MIL-STD-1553 B bus is a relatively common bus in avionics systems.It has the advantages of good real-time performance and high reliability,and is widely used.In specific occasions such as building simulation test environment,conducting R&D,repair and maintenance of bus interface devices and systems,due to high price,poor flexibility,and waste caused by functional redundancy,the technical solution of using the 1553 B bus protocol chip to implement the bus test platform is not very suitable.In contrast,the use of FPGA plus bus driver to implement bus interface functions has advantages in cost and flexibility.In view of the above requirements,this paper carries out the research work of 1553 B bus interface logic design and verification.In this paper,combined with the MIL-STD-1553 B bus protocol,an in-depth analysis of the functional characteristics of the 1553 B bus interface logic is carried out.Adopting the top-down and modularization idea,the interface logic design is carried out using Verilog HDL.The whole interface logic architecture is divided into processor interface,protocol processing,interrupt control,Manchester coding and decoding and other functional parts.The key functions of processor interface,Manchester codec and signal cross clock domain are analyzed in detail.The protocol processing functions of BC,RT and MT are designed and implemented separately,which reduces the complexity of logic design.Based on the command list,BC can flexibly define each frame of messages and realize the characteristics of message cyclic transmission;RT adopts ping-pong double buffer mode,which has the ability to quickly process data;MT adopts a message filter table structure,which can selectively monitor and record bus messages.In order to ensure the correctness of the interface logic design,a functional verification platform for the interface logic was built.System Verilog was used to verify the five non-mode command messages,the three necessary mode commands and the special functions of the terminal.The verification result confirms the correctness of the interface logic function.A hardware verification test platform was built using the 1553 B test board,and the interface logic was verified for board-level communication.The results show that the designed 1553 B bus interface logic can realize the protocol processing functions of the three terminals and has good actual communication functions.
Keywords/Search Tags:1553B, Bus Controller, Remote Terminal, Monitor Terminal
PDF Full Text Request
Related items