Design Of Clock Tree Routing In Wide Operating Voltage Range Based On Wire Snaking

Low-power applications such as sensors and embedded systems in recent years have received widespread attention.Operating in Wide voltage range is a good way to reduce power consumption and meet the requirements of high performance.But as the supply voltage decreases,it also brings some problems.First,as the operating voltage gradually decreases,the gate delay increases continuously,but the wire delay is basically unchanged.Secondly,as the operating voltage decreases,the effect of process variations increases,and the threshold voltage fluctuations caused by the process variations easily cause gate delay fluctuations.In addition,the increase in the gate delay and the drastic variations of the delay will cause the clock skew to increase,thereby causing the hold time violations and preventing the circuit from working properly.In view of the above problems,when clock paths are increased the same delay by adjusting the loaddependent delay ratio of clock path to the same value,reducing the clock skew at low voltage mode,in the light of the influence of process variations,the target value of the load-dependent delay ratio is greater than the average value of the proportion of load-dependent delay is proposed,ensure that the number of buffer stages after inserting the buffers is the same,reduce the number of inserted buffers and improve the ability of resisting process variations.Moreover,the optimization problem of wire snaking is transformed into a multivariate non-linear programming problem,achieved to reduce the clock skew in other voltage modes without increasing the clock skew in nominal voltage mode.The test and comparative analysis of this design are based on the ISCAS89 benchmark and the ARM Cortex-M series processors.The simulation results of the experiments shows that the number of inserted buffers is reduced by an average of 57.89% compared with [28].Compared with the clock trees synthesized at nominal voltage mode,the clock skew is decreased by an average of 23.51% when the operating voltage is 0.5V,and the standard deviation of the clock skew is reduced by 12.37%,on average;the clock skew is decreased by an average of 9.95 % when the operating voltage is 0.3V,and the standard deviation of the clock skew is reduced by 4.22 %,on average.In addition,compared with the unoptimized clock tree,power consumption increased by 3.29%,on average.