Design And Implementation Of Hardware Accelerator For Aircrafts Key Points Detection

With the rapid development of artificial intelligence technology,more and more complex and tedious process based on human beings has been transferred to artificial intelligence to complete.In recent years,the development of remote sensing images technology has become increasingly completed.The fine-grained recognition of remote sensing images aircrafts targets based on deep learning has been imported in airport management,aircraft target recognition,and route monitoring and so on.Some aircraft belong to the same large category,and there are only slight differences between local positions between them.The method of distinguishing these slightly different aircraft is called fine-grained classification of aircraft targets.The method of finding these slightly different local locations is called aircraft keypoint detection.The fine-grained classification of remote sensing images aircrafts targets includes two stages,aircraft key points detection based on VGG-19 convolutional neural network and fine-grained classification of aircrafts based on partial fully connected.This paper focuses on FPGA acceleration of the first stage of aircraft key points detection.Firstly,based on the remote sensing images aircrafts dataset,the data is transformed to fixed-point,then the numerical range of the image characteristics of each layer is calculated,the data format of layers is determined,and the deep learning convolutional neural network algorithm is fixed-pointed rewritten.Secondly,we design the key operations of VGG-19 algorithm,such as high-performance convolution operations for which can reach a utilization rate of 80% of the MAC array in different layers,pooling and fully connection operations based on sharing the cache and calculation components,which take advantage of bandwidth also.Thirdly,through the analysis and integration of the three computing schemes,the final design scheme was determined and performance evaluation and implementation were performed.The performance can reach 17.75 time of the accelerator was compared with the CPU platform,the experiments result showed that our work could achieve 3 the performance than CPU platform.Finally,to facilitate data correctness verification,early performance evaluation,and rapid application deployment,we designed and implemented a set of tool chains including network description file parsing,hardware executed data generation,instructions and address generation and error locating.