The Design Of An Analog Front-end For 3-dimensional Ultrasound Imaging

The development of society gives rise to a significant change of people’s lifestyle and their eating style.Overwhelming intake of sugar and fat gives rise to a surging possibility for people to get cardiovascular diseases.As a common way of diagnosis,ultrasonic cardiogram is popular because it is radiation-free,non-invasive and threedimensional imaging and even real-time imaging.The quality of imaging conventional transthoracic echocardiography(TTE)is quite vulnerable to the body and diseases of the patients themselves.On the contrary,transesophageal ultrasound echocardiography(TEE)helps people observing heart from its back,thereby eliminating the introducing of interference of bones and lungs and hence giving rise to a more satisfying resolution than its counterpart.Plus,more tissues,structures and some diseases can be detected with TEE.To realize a TEE imaging system with satisfying imaging quality,a 2-dimensional transducer array with great dimension should be employed.Also,the receiving circuits of every channel should have a power consumption under 1m W to avoid any possible harm to patients.What’s more,the probe itself should be small enough to be put into esophageal.Therefore,an analog front-end(AFE)with good resolution,low power consumption and small size is necessary for TEE applications.Though the existed pitch-matched digital subarray beamforming technique reduces the active area of the AFE of TEE system,it requires for an ADC for every single receiving transducer costing considerable amount of power consumption and chip area.In this work,a modified pitch-matched digital subarray beamforming technique is proposed to realize the object of the sharing of a single SAR ADC among4 transducer units.Based on the proposed structure and the characteristic of the attenuation of ultrasound,the requirement of design of time-gain compensation(TGC)module is defined.Then,the amplifier in TGC is analyzed and designed.The next step is the design of the SAR ADC.First,the total capacitance and structure of the DAC array is determined.Then,a bootstrapped sampling switch is designed with the parasitic capacitance deteriorating the sampling linearity blocked with some techniques.Also,a fully dynamic comparator is analyzed and designed to realize a low input-referred noise and adequate speed and resolution.Finally,a bypass-window algorithm is employed to lower the power consumption and the size of window is selected based on the postsimulation.This work is designed under a 130 nm standard CMOS technology.The simulation is performed in Hspice and Spectre simulators.The post-simulation results reveals that with the standard power supply and at the tt corner@25℃,the proposed SAR ADC has an SFDR of 74.01 d B,an SNDR of 58.94 d B and ENOB with 9.50 bits when it operates at a sampling rate of 100MS/ and samples an sinusoidal input with frequency of49.71 MHz and magnitude of 0.6·0.89 V.When the frequency of the input sinusoidal signal is 5MHz,the output spectrum reveals that the AFE has an SFDR of 58.94 d B,an SNDR of 56.64 d B and an ENOB of 8.78 bits.When the system quantifies a standard ultrasound signal,the average power consumption of the whole system is 4.1m W.The active area of the proposed circuit is 425μm×185μm.