Design And Digital Realization Of SiC-MOSFET-based Shunt Active Power Filter With 100kHz Switching Frequency

With the continuous development of more-electric aircraft,electrical equipments in the aircraft have been increased in large quantities,so that the harmonic problem in the aircraft power grid is becoming more and more serious.Because the fundamental frequency of the aircraft power grid is as high as 400 Hz,so the frequency of the fifth harmonic current can become 2 kHz.Limited by the traditional Si device and the slow DSP,the switching frequency of the traditional shunt active power filter(SAPF)is relatively low,so that the current control bandwidth cannot be designed very high to compensate the harmonic current in the 400 Hz power grid.With the maturation of new Si C device and high-speed DSP,the realization conditions of high-switching-frequency SAPF have been satisfied and it is possible to improve the harmonic compensation performance of SAPF by increasing the switching frequency.For the main circuit design of SAPF,a LCL filter,whose resonance was suppressed by passive damping,was used as the output filter of SAPF at first.Then the parameters of SAPF capacity,output filter and DC-bus capacitor are design.For the control strategy of SAPF,double closed-loop control of DC voltage and output current was used.A PI controller was adopted for the DC voltage control,and PI controller or PI combined with repetitive controller were adopted for the ouput cuurent control.Meanwhile,the parameters of these controllers were designed in this paper.Finally,the validity of main circuit design and control system design is verified by simulation.Digital realization of SAPF is one of the difficulties with the switching frequency increased to 100 kHz.As the part of harmonic extraction,traditional recursive discrete Fourier transform(RDFT),which needs more computing resource,was improved in this paper.By calculating RDFT to extract sextuple-frequency harmonic components after synchronous rotation coordinate transformation and reducing the half number of iterations,the computation time of the harmonic extraction is reduced by two-thirds and dynamic delay of RDFT algorithm is improved.Then digital signal processor(DSP)selected TMS320F28377 D which has 200 MHz clock speed and dual-core processor.By designing a multithreading digital method and assigning the computing tasks reasonably,the finite computing resource could be fully utilized.Finally,a SAPF experimental prototype with 100 kHz switching frequency and 10 k VA capacity is manufactured to verify the validity of the proposed design methods.