Design And Implementation Of A Reconfigurable LS＿SVM Accelerator

In recent years,as the feature size approaches the physical limit,the leakage power consumption rises sharply.Simply relying on the law of proportional scaling,Moore’s Law is difficult to move forward.How to further improve the performance of the chip under such circumstances has always been a focus of research in the industry,and reconfigurable computing makes it possible to further improve the performance of the chip.This thesis combines the current research hotspot:machine learning algorithm,focusing on the least squares support vector machine(LS_SVM)algorithm,and carries out the research on hardware acceleration using reconfigurable technology.Focusing on the hardware acceleration of the LS_SVM algorithm,this paper mainly accomplishes the following two aspects:First,using the reconfigurable technology,the hardware architecture of the LS_SVM training algorithm and the decision algorithm can be mapped on the same set of storage resources and computing resources through the coarse-grained configurable mode,and the SystemC system modeling of the reconfigurable LS_SVM accelerator is completed.The accelerator model includes two parts:the LS SVM trainer and the LS_SVM decision machine.Based on the reconfigurable LS-SVM accelerator model,the training convergence speed under different kernel functions is evaluated.For the same training samples,the hardware-friendly kernel function is 30%-40%faster than the Gaussian kernel function,and the hardware-friendly kernel is more easy to be implemented,but it does not affect the final classification accuracy.This model can further guide subsequent hardware implementations.Second,the hardware accelerator for the reconfigurable LS_SVM decision machine is designed.The LS_SVM decisionmachine is mainly composed offourparts:power value calculation module,exponential solution module,multiply-accumulate tree module and label judgment module.The power value calculation module and the exponential solution module respectively adopt 16 parallel and 32 parallel circuits;The cumulative selection module in the tree module is optimized for different training sample numbers,and can support any number of training samples to perform the accumulation operation.The reconfigurable LS_SVM decision machine is functionally verified in the Xilinx development board UltraScale XCVU440.The clock frequency is up to 125MHz,the classification accuracy is over 97%,and the time to complete the decision is in the order of milliseconds,which can meet the application requirements.The reconfigurable design method is a general method for building machine learning accelerators.With the popularity of machine learning acceleration hardware,this method will also be more widely used.