Self-modulated Planar Growth,Property Engineering And Device Application Of Uniform Ge/Si Superlattice Nanowires

Silicon-based integrated circuits are the cornerstone of the modern information society and play an extremely important role in social development.The rapidly iterating frontier technology of the silicon-based semiconductor industry directly affects the national economic development and has always been the focus of attention in the national economy and national defense and security fields.After decades of development,the miniaturization of integrated circuits generally follows Moore’s Law.However,the"top-down"etching technology is facing huge lithography bottlenecks and expensive preparation cost due to the influence of short channel effect and quantum tunneling.Recently,the domestic high-end chip manufacturing industry is facing malicious blockade by foreign companies,thus it is necessary to find alternative way to explore new micro-nano channel preparation technology,so as to break the technological monopoly and blockade of my country by western forces.Among them,quasi-one-dimensional semiconductor nanowires have unique characteristics of optoelectronics,transport and quantum confinement effects compared to bulk materials,and are widely investigated and applied to develop a new generation of high-performance photoelectric detection,flexible electronics,bio-technology sensing and device applications,as Field Effect Transistor for example.Therefore,it is a hot topic to prepare the high-quality semiconductor nanowire channel devices through low-temperature,high-efficiency,and abundant"bottom-up"growth technology.According to the traditional VLS growth mechanism,various nanowire structures with fine size,rich morphology,and controllable composition can be prepared,and a series of prototype functional devices have been successfully demonstrated.However,most of the nanowires grown by the VLS mechanism are vertical structures and need to be transferred and positioned on a flat substrate to complete the connection and integration of electrical devices.It is difficult to achieve precise positioning in batches,compatible with mature existing process platforms and large-scale integrated preparation,which limits the practical application of nanowires in high-performance electronic devices.In this thesis,we developed a new approach to directly grow a Ge/Si SNWs array,by usingα-Ge/α-Si heterogeneous laminated precursor,based on our IPSLS growth mechanism.In addition,the morphological structure and composition distribution characteristics of Ge/Si SNWs were systematically studied by using scanning electron microscope（SEM）and Transmission Electron Microscope（TEM）,respectively.We also investigated electrical performances of the fabricated Ge/Si SNWs channel FET devices.Interestingly,we found that the Ge/Si SNWs can be selectively etching by Inductive Coupled Plasma（ICP）,which was combined with heterogeneous light-emitting quantum dots to expand a new idea for preparing silicon-based nano-light sources.Finally,we proposed a new strategy for the preparation of fin structure channels by using the superlattice nanowires due to the reliable positioning growth and selective etching technology of Ge/Si SNWs.Specifically,the main work and innovations of this paper are as follows:1.Based on the growth mechanism of IPSLS,the amorphous Ge/Si heterogeneous bilayer precursor control the indium nano-droplet technology has been developed.The self-automated growth of uniform Ge/Si SNWs,has been accomplished via an In droplet-mediated transformation of uniform amorphous a-Si/a-Ge bilayer thin films.The diameter of the nanowires is uniform,and the thickness of each layer of Ge/Si can be controlled at about 20 nm,and it can be accurately positioned on a plane substrate.2.A superlattice structure with alternating layers of Ge/Si has been identified by the in-depth study of the morphology and composition characteristics of the nanowires using a variety of characterization methods.The superlattice nanowires FETs are prepared,and the electrical properties of the device are studied.The Ge/Si SNWs show good conductivity,and the I_ds reach to 10μA under V_ds=2 V.By selectively etching crystalline Ge on superlattice nanowires,a new technology for accurately positioning and assembling quantum dot light sources on silicon-based nanowires is proposed.3.A strategy for fabricating Fin FET on planar Ge/Si SNWs is proposed,which will provide a novel method for fabricating nano-conducting channels of FETs.The channel width and the channel length of nano-conducting channels can be adjusted to1～20 nm and 28～300 nm,respectively.This method is compatible with the planar silicon process platform and can achieve positioning integration,and is expected to develop into an advanced technology for preparing Fin FET similar to the 28 nm process.This research lays a key foundation for exploring new dynamic control methods for nanodroplets and achieving the application of high-performance Field-Effect Transistor devices.