Research On Key Technologies Of Blind Vision Assistance System Based On Pynq Platform

There are currently about 285 million visually impaired people in the world.They are gradually marginalized by society due to the loss of vision,an important source of information.Therefore,it is of great social and engineering significance to apply visual image processing technology to blind assistance systems,which helps them get better information from their surroundings.With the development of deep learning,target detection algorithms based on convolutional neural networks have begun to be applied to blind visual aid systems,which are superior to traditional visual image processing techniques in recognition rate and robustness.However,because convolutional neural network operations involve a large number of calculations and frequent data reading and writing,the algorithm encountered problems of poor real-time performance and excessive power consumption when it was transplanted to embedded systems with limited resources.In view of the above problems,this paper studies the key technology of designing the hardware acceleration circuit of the convolutional neural network by combining the optimization of the storage system and the computing structure.The main research contents of this article include:1?Study the new arrangement of feature data and weight data in external memory in convolutional neural network.The new arrangement combines the parallel computing structure of the input channel and the output channel,and is adapted to the data transmission characteristics of the Advanced Extensible Interface(AXI)bus.It can provide storage system support for the hardware acceleration circuit design to effectively reduce the transmission delay.2?Study the design of parallel operation of pooling unit.This scheme decomposes the pool computing structure into two parts: row pooling and column pooling,and combines parallelize operations of input channels.Allows data to be transmitted between the pooling unit and the external memory in the form of a data stream,and simplifies pooling combinational logic circuit to save hardware resources.This scheme effectively improves the hardware circuit throughput and utilization rate of arithmetic unit.3?Study the design scheme of parallel operation of convolution unit.This scheme optimizes the algorithm structure of the convolution operation and combines it with the twodimensional parallel expansion of the input channel and output channel.Transforming a large number of serial multiply-add operations into matrix multiplications to accelerate computations in parallel,which can effectively reduce the operation delay.The optimized algorithm structure data access mode is more flexible,which can be reused by convolutional layers of different sizes,and the utilization rate of computing power unit is guaranteed.4?Based on the solution 2 and 3,combining convolution integration solutions and data reuse to further improve bandwidth utilization,FPGA-based convolution operation unit and pooling operation hardware acceleration circuit are implemented.And build a hardware system.This design uses the PYNQ-Z2 heterogeneous development platform to successfully implement the hardware acceleration of the convolutional neural network in the YOLOv2 algorithm,and completes the prototype system building and testing in the software environment.The experimental results show that the performance of 31.25GOPS/s is achieved on the PYNQ-Z2 platform,the total power on chip is only 2.763 W,and the average utilization of computing resources is 89%..