| Various logic transformation techniques have been developed to optimize different aspects of Boolean circuit designs, such as area, speed, power and soft error rate. They range from algebraic operations to Boolean operations. Among the Boolean optimization techniques, rewiring is known to be as robust and flexible as others. Its idea is to replace a set of existing wires (target wires) in a circuit with another set of additional wires (alternative wires) which do not exist in the circuit originally. Hence, it is suitable for the design and manufacturing processes in today's nano-metre era in which wiring has become a dominating factor. In this thesis, a more general rewiring scheme based on the concepts of error cancellation as well as the traditional rewiring schemes were studied. Applications of rewiring and error cancellation concepts on power reduction and fault tolerance were experimented. Firstly, rewiring was adopted as a tool to minimize the area and power of clock gated circuits. Secondly, error-cancellation- based rewiring and traditional clock gating were integrated as a new kind of clock gating scheme. Lastly, a fault tolerance scheme based on redundant wire addition was developed. |
