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Efficient design for high-speed network and multiprocessor architectures

Posted on:1995-01-19Degree:Ph.DType:Thesis
University:University of MinnesotaCandidate:Tong, Sheau-RuFull Text:PDF
GTID:2478390014991139Subject:Computer Science
Abstract/Summary:
With the advancement of VLSI/WSI and optical technologies, high-performance communication networks (ranging from wide/local area networks to multiprocessor systems) have become a reality. Such communication networks are capable of supporting high bandwidth transfers, a large number of attached stations and the integration of distributed heterogeneous computing resources. This thesis concerns with the following two areas which fall under the category of high performance communications: High-Speed Networks for local or metropolitan area and Multi-stage Interconnection Networks (MINs) for shared-memory multiprocessor systems.;For high-speed local/metropolitan area networks, we focus on the ones based on the optical passive star architecture. Such networks are capable of supporting enormous bandwidth in the optical domain for a large number of stations. We investigate fundamental design principles of media access protocols and propose several design methodologies. The proposed protocols require a static wavelength setting and fixed wavelength or slowly tunable transmitters/receivers (which are cheaper and more stable compared with fast tunable transmitters/receivers). They also employ the hybrid scheme of Wavelength and Time Division Multiplexing (WTDM). Tradeoffs of several important design parameters are discussed, and performance of different designs under different environments is analyzed. This analysis leads to several optimal design strategies.;MINs have been recognized as one of the most cost-effective switching fabrics for large-scale multiprocessor systems. However, a type of nonuniform traffic, called hot-spot traffic, may occur in the parallel programming paradigm and cause a congestion phenomenon in MINs which may result in a system-wide performance degradation. To remedy this deficiency, we propose an enhanced MIN architecture. Two capabilities, packet diverting and limited combining, are proposed and their cooperative effects are studied. Both analysis and simulation show that such a design can alleviate congestion and improve performance.
Keywords/Search Tags:Multiprocessor, Performance, Networks, High-speed
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