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Optimization of queueing performance and design variables in a single -bus shared -memory system with application to MPEG-2 video decoder system

Posted on:2003-02-02Degree:Ph.DType:Thesis
University:Santa Clara UniversityCandidate:Li, Jui-HuaFull Text:PDF
GTID:2468390011981619Subject:Electrical engineering
Abstract/Summary:
This thesis presents a methodology of decision-making for the design variables, embedded I/O buffer sizes, in a single-bus shared-memory system. The decision is made with the aid of a queueing model, simulation, and an optimization algorithm. A queueing model is used to simulate the system behavior and to obtain the system response. The generalized queueing model is simulated to cover two cases: independent processing units and pipelined processing units in a shared-memory environment. The objective is to obtain the best performance with the optimized embedded buffers in the system. Therefore, an algorithm is developed to find the optimal solution efficiently by exploring the correlation between buffers and system performance. The local optimum is guaranteed. The method can be widely applied to many applications.;In this thesis, an MPEG-2 video decoder is used as the major case study. The proposed decoder architecture and controller scheme achieve real-time performance for main profile at main level (MP ML). A generalized queueing model is proposed to describe the real system. This model can be applied not only to the MPEG-2 codec system, but also to other MPEG applications, like HDTV and MPEG-4. Two important issues, bus bandwidth and system performance, are analyzed in detail to explore the impact of the design variables on the system. The proposed methodology is then used to properly determine design variables, I/O buffer sizes, and to optimize system performance.;The experimental results show that this methodology produces a dramatic increase in system performance. In one simulation, the system performance is increased by 44% and the bus bandwidth is reduced by 19% with the optimal buffer sizes. Another experiment shows that the optimal buffer setting simply reduces the complexity of bus design. The proposed algorithm indeed provides a best solution for I/O buffers to improve the system performance and to utilize the hardware resource without any increased cost.
Keywords/Search Tags:System, Performance, Design variables, I/O, MPEG-2, Bus, Buffer, Queueing
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