Development of an FPGA based wavelet transformer for the compression of raw SAR data

This thesis describes the design and implementation of the one-dimensional (1-D) discrete wavelet transform (DWT) using filter banks as a custom computing engine (CCE), using a Xilinx field programmable gate array (FPGA) for the compression of raw synthetic aperture radar (SAR) data.; The compression of raw SAR data has been a topic of interest to researchers for many years as the spaceborne SAR instrument generates an enormous amount of coherent information, which must be transmitted back to Earth for processing into the final SAR product. The goal of any new raw SAR data compression technique is to transmit the highest fidelity data from the radar satellite within the downlink bandwidth constraints. Since developing a theoretical compression technique is not a complete solution to the problem, the technique must be realizable in the hardware available for placement on the radar satellite. To this end, 2-D transform techniques are not practical due to the large on-board memory requirements. The implementation must not only be low in computational complexity, but must also be able to handle the ever increasing throughput demands of the radar.; Experimental results of the 1-D DWT technique on pre-conditioned raw SAR data in MatLab show that the best performing wavelet basis function is Daubechies-2, but that there is very little difference between all standard wavelet basis. The CCE implementation of the 1-D DWT technique gives an average SQNR of 8.95 dB on the five test sets which is 0.4 dB lower than that the average SQNR of BAQ.