Post-CMOS micromachining of surface and bulk structures

This thesis describes fabrication of the micro-electro-mechanical system (MEMS) through post Complementary-Metal-Oxide-Semiconductor (CMOS) micromachining. It focuses on device fabrication instead of device designs. The reactive-ion-etch (RIE) and deep-reactive-ion-etch (DRIE) are key technologies in this process flow. Surface micromachining of the thin-film dielectric material and bulk micromachining of the Si substrate are discussed in detail. Fundamentals of the RIE and DRIE dry etch, the methodology to characterize these process techniques and the design of experiments (DOE) to discover processing windows for post-CMOS micromachining are illustrated. Experimental results of the processing characterization are translated to MEMS design rules. These rules serve as a protocol to qualify the process as a common platform and to verify MEMS device designs to be built on this platform. Migrations of post-CMOS micromachining have been demonstrated with advances of CMOS fabrication: from a 0.5 μm process to a 0.18 μm process, from an aluminum (Al) interconnect silicon-dioxide (SiO₂) dielectric process to a copper (Cu) interconnect low-K dielectric process. Different CMOS foundry services in the United States, Europe, and Asia, have been selected to successfully fabricate MEMS devices. Starting with small chips at the size of 2 mm x 2 mm, post-CMOS micromachining can be performed at the wafer scale with an add-on low resolution photoresist mask layer. An integrated dicing scheme into the post-CMOS process flow has been documented. A wet chemical cleaning step can be inserted into the process flow to remove etch by-products in RIE therefore improves the quality of the process. The application in areas of the high-performance inertial sensor and high-quality passive radio-frequency (RF) components are demonstrated.