| Reduction of the MOS gate insulator thickness below 3.5 nm results in increased current through the gate, due to the direct tunneling mechanism. Recent fabrication of MOS devices with gate insulators as thin as 1.1 nm has increased the role of direct tunneling in determining MOSFET device performance, design, characterization, and reliability. Despite its growing importance, a capability for simulating the effects of direct tunneling in MOS devices is not currently available in a vertically integrated process/device/circuit simulation environment. Incorporation of a direct-tunneling model into PISCES will provide MOSFET designers with the capability to develop new scaling rules and optimization methods for deep-submicron devices while taking carrier tunneling into account. This thesis develops the physical models and boundary conditions for tunneling in MOS devices that are appropriate for incorporation into a new MOSFET tunneling device simulator—Tunnel-PISCES. Next, this thesis outlines how numerical algorithms in a classical drift-diffusion device simulator can be modified to incorporate a direct-tunneling model. Finally, results performed using Tunnel-PISCES are presented. The simulation results compare favorably with available experimental data. The results indicate that the Tunnel-PISCES simulation environment is indispensible to designers of deep-submicron ultrathin-oxide MOS devices in the presence of significant gate-oxide tunneling. |
