Synthesis of mixed-signal systems based on rapid prototyping

This dissertation presents a methodology for behavioral synthesis of analog and mixed signal systems based on rapid prototyping followed by technology retargeting. Rapid prototyping with field-programmable devices enables fast implementation of a function-compliant hardware prototype, while technology retargeting converts the functional prototype to an ASIC. The synthesis environment comprises of field-programmable mixed-signal prototyping hardware integrated with the design tools for automated synthesis of mixed-signal systems from high-level behavioral specifications. The prototyping system is composed of field-programmable analog arrays (FPAAs) and field-programmable gate arrays (FPGAs) on which the synthesized designs are implemented and validated. Mixed-signal functionality of the system. This is represented in an intermediate format suitable for synthesis. Identification of the portions to be implemented in analog and digital domains follows. The partitioned design must best satisfy the system's architectural and performance constraints. And finally, the analog and digital subsystems are synthesized for the target FPAA and FPGA technologies respectively.; Synthesis of mixed-signal designs from behavioral specifications must address analog-digital partitioning. We begin with the system behavior specified based on signal/data-flow. Our intermediate format for representation, called the Mixed Signal Flow Graph, is based on the time-amplitude characterization of signals: (1) continuous time, continuous amplitude, (2) continuous time, discrete amplitude, (3) discrete-time, continuous amplitude, and (4) discrete time, discrete amplitude. The behavior in each domain is represented by a connected network of behavioral blocks.; The behavior of an analog system is represented as a signal flow graph (SFG), where nodes represent operations (transfer functions and non-linear functions) on signals and edges represent signal flow. Library binding or technology mapping transforms the given behavior into a netlist of cells from the target library, optimized for performance.; Every component of the validated design is mapped to a ASIC component that has same functionality, and its parameters are used to derive the ASIC component parameters. Thus retargeting produces an ASIC netlist of component-level functional equivalents. (Abstract shortened by UMI.)...