Reverse converter design based on the New Chinese Remainder Theorem II using parallel prefix adder

Properties of the Residue Number System (RNS) such as parallelism, carry-free operations, and fault tolerance, make it a highly effective method to perform high speed arithmetic. However, reverse conversion is a major drawback due to its time-consuming modulo operations, especially when the number of moduli in the moduli set is more than three. In this project, the residue number system reverse converter, based on the New Chinese Remainder Theorem II (CRT-II) for the 4-moduli set {2n-1 -- 1, 2 n -- 1, 2n, 2n + 1} is presented. The special properties of the moduli set are utilized by the CRT-II to produce an architecture that eliminates the delay factor in reverse converters and can be easily implemented in hardware. Parallel prefix adders are analyzed and induced into the reverse converter. In terms of delay and area, the VLSI implementation results demonstrate the comparable advantage of the reverse converters with the parallel prefix adder and carry propagate adder.